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17#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
18#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
19#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
20#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
21#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
22#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
23#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
27#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
28#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
29#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
32#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
33#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
34#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
37#define SET_MEM_ATTR_DATA_PERM_MASK 0x3
38#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
39#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
40#define SET_MEM_ATTR_DATA_PERM_RW 1
41#define SET_MEM_ATTR_DATA_PERM_RO 3
43#define SET_MEM_ATTR_CODE_PERM_MASK 0x1
44#define SET_MEM_ATTR_CODE_PERM_SHIFT 2
45#define SET_MEM_ATTR_CODE_PERM_X 0
46#define SET_MEM_ATTR_CODE_PERM_XN 1
48#define SET_MEM_ATTR_MAKE_PERM_REQUEST(d_perm, c_perm) \
49 ((((c_perm) & SET_MEM_ATTR_CODE_PERM_MASK) << SET_MEM_ATTR_CODE_PERM_SHIFT) | \
50 (( (d_perm) & SET_MEM_ATTR_DATA_PERM_MASK) << SET_MEM_ATTR_DATA_PERM_SHIFT))
53#define ARM_SVC_SPM_RET_SUCCESS 0
54#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
55#define ARM_SVC_SPM_RET_INVALID_PARAMS -2
56#define ARM_SVC_SPM_RET_DENIED -3
57#define ARM_SVC_SPM_RET_NO_MEMORY -5
59#define SPM_MAJOR_VERSION 0
60#define SPM_MINOR_VERSION 1