TianoCore EDK2 master
CpuDxe.c
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1
10#include "CpuDxe.h"
11
12#include <Guid/IdleLoopEvent.h>
13
14BOOLEAN mIsFlushingGCD;
15
44EFIAPI
48 IN UINT64 Length,
49 IN EFI_CPU_FLUSH_TYPE FlushType
50 )
51{
52 switch (FlushType) {
53 case EfiCpuFlushTypeWriteBack:
54 WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
55 break;
56 case EfiCpuFlushTypeInvalidate:
57 InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
58 break;
59 case EfiCpuFlushTypeWriteBackInvalidate:
60 WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
61 break;
62 default:
63 return EFI_INVALID_PARAMETER;
64 }
65
66 return EFI_SUCCESS;
67}
68
79EFIAPI
82 )
83{
84 ArmEnableInterrupts ();
85
86 return EFI_SUCCESS;
87}
88
99EFIAPI
102 )
103{
104 ArmDisableInterrupts ();
105
106 return EFI_SUCCESS;
107}
108
123EFIAPI
126 OUT BOOLEAN *State
127 )
128{
129 if (State == NULL) {
130 return EFI_INVALID_PARAMETER;
131 }
132
133 *State = ArmGetInterruptState ();
134 return EFI_SUCCESS;
135}
136
154EFIAPI
157 IN EFI_CPU_INIT_TYPE InitType
158 )
159{
160 return EFI_UNSUPPORTED;
161}
162
164EFIAPI
167 IN EFI_EXCEPTION_TYPE InterruptType,
168 IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
169 )
170{
171 return RegisterInterruptHandler (InterruptType, InterruptHandler);
172}
173
175EFIAPI
178 IN UINT32 TimerIndex,
179 OUT UINT64 *TimerValue,
180 OUT UINT64 *TimerPeriod OPTIONAL
181 )
182{
183 return EFI_UNSUPPORTED;
184}
185
194VOID
195EFIAPI
197 IN EFI_EVENT Event,
198 IN VOID *Context
199 )
200{
201 CpuSleep ();
202}
203
204//
205// Globals used to initialize the protocol
206//
207EFI_HANDLE mCpuHandle = NULL;
213 CpuInit,
217 0, // NumberOfTimers
218 2048, // DmaBufferAlignment
219};
220
221STATIC
222VOID
223InitializeDma (
224 IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol
225 )
226{
227 CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();
228}
229
231CpuDxeInitialize (
232 IN EFI_HANDLE ImageHandle,
233 IN EFI_SYSTEM_TABLE *SystemTable
234 )
235{
236 EFI_STATUS Status;
237 EFI_EVENT IdleLoopEvent;
238
239 InitializeExceptions (&mCpu);
240
241 InitializeDma (&mCpu);
242
243 Status = gBS->InstallMultipleProtocolInterfaces (
244 &mCpuHandle,
245 &gEfiCpuArchProtocolGuid,
246 &mCpu,
247 NULL
248 );
249
250 //
251 // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()
252 // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go
253 // after the protocol is installed
254 //
255 mIsFlushingGCD = TRUE;
256 SyncCacheConfig (&mCpu);
257 mIsFlushingGCD = FALSE;
258
259 // If the platform is a MPCore system then install the Configuration Table describing the
260 // secondary core states
261 if (ArmIsMpCore ()) {
263 }
264
265 //
266 // Setup a callback for idle events
267 //
268 Status = gBS->CreateEventEx (
269 EVT_NOTIFY_SIGNAL,
270 TPL_NOTIFY,
272 NULL,
273 &gIdleLoopEventGuid,
274 &IdleLoopEvent
275 );
276 ASSERT_EFI_ERROR (Status);
277
278 return Status;
279}
UINT64 UINTN
VOID *EFIAPI WriteBackDataCacheRange(IN VOID *Address, IN UINTN Length)
VOID *EFIAPI InvalidateDataCacheRange(IN VOID *Address, IN UINTN Length)
VOID *EFIAPI WriteBackInvalidateDataCacheRange(IN VOID *Address, IN UINTN Length)
EFI_STATUS EFIAPI CpuGetInterruptState(IN EFI_CPU_ARCH_PROTOCOL *This, OUT BOOLEAN *State)
Definition: CpuDxe.c:124
VOID EFIAPI IdleLoopEventCallback(IN EFI_EVENT Event, IN VOID *Context)
Definition: CpuDxe.c:196
EFI_STATUS EFIAPI CpuRegisterInterruptHandler(IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler)
Definition: CpuDxe.c:165
EFI_STATUS EFIAPI CpuGetTimerValue(IN EFI_CPU_ARCH_PROTOCOL *This, IN UINT32 TimerIndex, OUT UINT64 *TimerValue, OUT UINT64 *TimerPeriod OPTIONAL)
Definition: CpuDxe.c:176
EFI_STATUS EFIAPI CpuDisableInterrupt(IN EFI_CPU_ARCH_PROTOCOL *This)
Definition: CpuDxe.c:100
EFI_STATUS EFIAPI CpuInit(IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_INIT_TYPE InitType)
Definition: CpuDxe.c:155
EFI_STATUS EFIAPI CpuFlushCpuDataCache(IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS Start, IN UINT64 Length, IN EFI_CPU_FLUSH_TYPE FlushType)
Definition: CpuDxe.c:45
EFI_STATUS EFIAPI CpuEnableInterrupt(IN EFI_CPU_ARCH_PROTOCOL *This)
Definition: CpuDxe.c:80
EFI_STATUS RegisterInterruptHandler(IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler)
Definition: Exception.c:93
VOID EFIAPI PublishArmProcessorTable(VOID)
Definition: CpuMpCore.c:44
#define NULL
Definition: Base.h:312
#define STATIC
Definition: Base.h:264
#define TRUE
Definition: Base.h:301
#define FALSE
Definition: Base.h:307
#define IN
Definition: Base.h:279
#define OUT
Definition: Base.h:284
EFI_CPU_FLUSH_TYPE
Definition: Cpu.h:24
EFI_CPU_INIT_TYPE
Definition: Cpu.h:34
VOID(EFIAPI * EFI_CPU_INTERRUPT_HANDLER)(IN CONST EFI_EXCEPTION_TYPE InterruptType, IN CONST EFI_SYSTEM_CONTEXT SystemContext)
Definition: Cpu.h:52
VOID EFIAPI CpuSleep(VOID)
#define ASSERT_EFI_ERROR(StatusParameter)
Definition: DebugLib.h:440
INTN EFI_EXCEPTION_TYPE
Definition: DebugSupport.h:35
UINT64 EFI_PHYSICAL_ADDRESS
Definition: UefiBaseType.h:49
RETURN_STATUS EFI_STATUS
Definition: UefiBaseType.h:28
VOID * EFI_EVENT
Definition: UefiBaseType.h:36
VOID * EFI_HANDLE
Definition: UefiBaseType.h:32
#define EFI_SUCCESS
Definition: UefiBaseType.h:111
EFI_BOOT_SERVICES * gBS
EFI_STATUS EFIAPI CpuSetMemoryAttributes(IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
Definition: CpuDxe.c:371