TianoCore EDK2 master
Loading...
Searching...
No Matches
Cpucfg.h
Go to the documentation of this file.
1
9#ifndef CPUCFG_H_
10#define CPUCFG_H_
11
18#define CPUCFG_REG0_INFO 0x0
19
24typedef union {
25 struct {
29 UINT32 PRID : 32;
30 } Bits;
34 UINT32 Uint32;
35} CPUCFG_REG0_INFO_DATA;
36
43#define CPUCFG_REG1_INFO 0x1
44
49typedef union {
50 struct {
58 UINT32 ARCH : 2;
63 UINT32 PGMMU : 1;
67 UINT32 IOCSR : 1;
72 UINT32 PALEN : 8;
77 UINT32 VALEN : 8;
82 UINT32 UAL : 1;
87 UINT32 RI : 1;
92 UINT32 EP : 1;
96 UINT32 RPLV : 1;
101 UINT32 HP : 1;
106 UINT32 IOCSR_BRD : 1;
111 UINT32 MSG_INT : 1;
115 UINT32 Reserved : 5;
116 } Bits;
120 UINT32 Uint32;
121} CPUCFG_REG1_INFO_DATA;
122
129#define CPUCFG_REG2_INFO 0x2
130
135typedef union {
136 struct {
141 UINT32 FP : 1;
146 UINT32 FP_SP : 1;
151 UINT32 FP_DP : 1;
156 UINT32 FP_ver : 3;
161 UINT32 LSX : 1;
166 UINT32 LASX : 1;
171 UINT32 COMPLEX : 1;
176 UINT32 CRYPTO : 1;
181 UINT32 LVZ : 1;
186 UINT32 LVZ_ver : 3;
191 UINT32 LLFTP : 1;
195 UINT32 LLTP_ver : 3;
200 UINT32 LBT_X86 : 1;
205 UINT32 LBT_ARM : 1;
210 UINT32 LBT_MIPS : 1;
215 UINT32 LSPW : 1;
220 UINT32 LAM : 1;
224 UINT32 Reserved : 9;
225 } Bits;
229 UINT32 Uint32;
230} CPUCFG_REG2_INFO_DATA;
231
238#define CPUCFG_REG3_INFO 0x3
239
244typedef union {
245 struct {
250 UINT32 CCDMA : 1;
255 UINT32 SFB : 1;
260 UINT32 UCACC : 1;
265 UINT32 LLEXC : 1;
270 UINT32 SCDLY : 1;
274 UINT32 LLDBAR : 1;
279 UINT32 ITLBT : 1;
284 UINT32 ICACHET : 1;
288 UINT32 SPW_LVL : 3;
293 UINT32 SPW_HP_HF : 1;
298 UINT32 RVA : 1;
302 UINT32 RVAMAX_1 : 4;
306 UINT32 Reserved : 15;
307 } Bits;
311 UINT32 Uint32;
312} CPUCFG_REG3_INFO_DATA;
313
320#define CPUCFG_REG4_INFO 0x4
321
326typedef union {
327 struct {
332 UINT32 CC_FREQ : 32;
333 } Bits;
337 UINT32 Uint32;
338} CPUCFG_REG4_INFO_DATA;
339
346#define CPUCFG_REG5_INFO 0x5
347
352typedef union {
353 struct {
358 UINT32 CC_MUL : 16;
363 UINT32 CC_DIV : 16;
364 } Bits;
368 UINT32 Uint32;
369} CPUCFG_REG5_INFO_DATA;
370
377#define CPUCFG_REG6_INFO 0x6
378
383typedef union {
384 struct {
389 UINT32 PMP : 1;
394 UINT32 PMVER : 3;
398 UINT32 PMNUM : 4;
402 UINT32 PMBITS : 6;
406 UINT32 UPM : 1;
410 UINT32 Reserved : 17;
411 } Bits;
415 UINT32 Uint32;
416} CPUCFG_REG6_INFO_DATA;
417
424#define CPUCFG_REG16_INFO 0x10
425
430typedef union {
431 struct {
436 UINT32 L1_IU_Present : 1;
441 UINT32 L1_IU_Unify : 1;
445 UINT32 L1_D_Present : 1;
450 UINT32 L2_IU_Present : 1;
455 UINT32 L2_IU_Unify : 1;
460 UINT32 L2_IU_Private : 1;
465 UINT32 L2_IU_Inclusive : 1;
469 UINT32 L2_D_Present : 1;
473 UINT32 L2_D_Private : 1;
478 UINT32 L2_D_Inclusive : 1;
483 UINT32 L3_IU_Present : 1;
488 UINT32 L3_IU_Unify : 1;
493 UINT32 L3_IU_Private : 1;
498 UINT32 L3_IU_Inclusive : 1;
502 UINT32 L3_D_Present : 1;
506 UINT32 L3_D_Private : 1;
511 UINT32 L3_D_Inclusive : 1;
515 UINT32 Reserved : 15;
516 } Bits;
520 UINT32 Uint32;
521} CPUCFG_REG16_INFO_DATA;
522
529#define CPUCFG_REG17_INFO 0x11
530#define CPUCFG_REG18_INFO 0x12
531#define CPUCFG_REG19_INFO 0x13
532#define CPUCFG_REG20_INFO 0x14
533
541typedef union {
542 struct {
546 UINT32 Way_1 : 16;
550 UINT32 Index_log2 : 8;
554 UINT32 Linesize_log2 : 7;
558 UINT32 Reserved : 1;
559 } Bits;
563 UINT32 Uint32;
564} CPUCFG_CACHE_INFO_DATA;
565#endif