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SmramSaveStateMap.h
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1
14#ifndef AMD_SMRAM_SAVE_STATE_MAP_H_
15#define AMD_SMRAM_SAVE_STATE_MAP_H_
16
20#define SMM_DEFAULT_SMBASE 0x30000
21
25#define SMM_HANDLER_OFFSET 0x8000
26
27// SMM-Revision Identifier for AMD64 Architecture.
28#define AMD_SMM_MIN_REV_ID_X64 0x30064
29
30#pragma pack (1)
31
35typedef struct {
36 // Padded an extra 0x200 bytes to match Intel/EDK2
37 UINT8 Reserved[0x200]; // fc00h
38 // AMD Save State area starts @ 0xfe00
39 UINT8 Reserved1[0xf8]; // fe00h
40 UINT32 SMBASE; // fef8h
41 UINT32 SMMRevId; // fefch
42 UINT16 IORestart; // ff00h
43 UINT16 AutoHALTRestart; // ff02h
44 UINT8 Reserved2[0x84]; // ff04h
45 UINT32 GDTBase; // ff88h
46 UINT64 Reserved3; // ff8ch
47 UINT32 IDTBase; // ff94h
48 UINT8 Reserved4[0x10]; // ff98h
49 UINT32 _ES; // ffa8h
50 UINT32 _CS; // ffach
51 UINT32 _SS; // ffb0h
52 UINT32 _DS; // ffb4h
53 UINT32 _FS; // ffb8h
54 UINT32 _GS; // ffbch
55 UINT32 LDTBase; // ffc0h
56 UINT32 _TR; // ffc4h
57 UINT32 _DR7; // ffc8h
58 UINT32 _DR6; // ffcch
59 UINT32 _EAX; // ffd0h
60 UINT32 _ECX; // ffd4h
61 UINT32 _EDX; // ffd8h
62 UINT32 _EBX; // ffdch
63 UINT32 _ESP; // ffe0h
64 UINT32 _EBP; // ffe4h
65 UINT32 _ESI; // ffe8h
66 UINT32 _EDI; // ffech
67 UINT32 _EIP; // fff0h
68 UINT32 _EFLAGS; // fff4h
69 UINT32 _CR3; // fff8h
70 UINT32 _CR0; // fffch
71} AMD_SMRAM_SAVE_STATE_MAP32;
72
76typedef struct {
77 // Padded an extra 0x200 bytes to match Intel/EDK2
78 UINT8 Reserved[0x200]; // fc00h
79 // AMD Save State area starts @ 0xfe00
80 UINT16 _ES; // fe00h
81 UINT16 _ESAttributes; // fe02h
82 UINT32 _ESLimit; // fe04h
83 UINT64 _ESBase; // fe08h
84
85 UINT16 _CS; // fe10h
86 UINT16 _CSAttributes; // fe12h
87 UINT32 _CSLimit; // fe14h
88 UINT64 _CSBase; // fe18h
89
90 UINT16 _SS; // fe20h
91 UINT16 _SSAttributes; // fe22h
92 UINT32 _SSLimit; // fe24h
93 UINT64 _SSBase; // fe28h
94
95 UINT16 _DS; // fe30h
96 UINT16 _DSAttributes; // fe32h
97 UINT32 _DSLimit; // fe34h
98 UINT64 _DSBase; // fe38h
99
100 UINT16 _FS; // fe40h
101 UINT16 _FSAttributes; // fe42h
102 UINT32 _FSLimit; // fe44h
103 UINT64 _FSBase; // fe48h
104
105 UINT16 _GS; // fe50h
106 UINT16 _GSAttributes; // fe52h
107 UINT32 _GSLimit; // fe54h
108 UINT64 _GSBase; // fe58h
109
110 UINT32 _GDTRReserved1; // fe60h
111 UINT16 _GDTRLimit; // fe64h
112 UINT16 _GDTRReserved2; // fe66h
113 // UINT64 _GDTRBase; // fe68h
114 UINT32 _GDTRBaseLoDword;
115 UINT32 _GDTRBaseHiDword;
116
117 UINT16 _LDTR; // fe70h
118 UINT16 _LDTRAttributes; // fe72h
119 UINT32 _LDTRLimit; // fe74h
120 // UINT64 _LDTRBase; // fe78h
121 UINT32 _LDTRBaseLoDword;
122 UINT32 _LDTRBaseHiDword;
123
124 UINT32 _IDTRReserved1; // fe80h
125 UINT16 _IDTRLimit; // fe84h
126 UINT16 _IDTRReserved2; // fe86h
127 // UINT64 _IDTRBase; // fe88h
128 UINT32 _IDTRBaseLoDword;
129 UINT32 _IDTRBaseHiDword;
130
131 UINT16 _TR; // fe90h
132 UINT16 _TRAttributes; // fe92h
133 UINT32 _TRLimit; // fe94h
134 UINT64 _TRBase; // fe98h
135
136 UINT64 IO_RIP; // fea0h
137 UINT64 IO_RCX; // fea8h
138 UINT64 IO_RSI; // feb0h
139 UINT64 IO_RDI; // feb8h
140 UINT32 IO_DWord; // fec0h
141 UINT8 Reserved1[0x04]; // fec4h
142 UINT8 IORestart; // fec8h
143 UINT8 AutoHALTRestart; // fec9h
144 UINT8 Reserved2[0x06]; // fecah
145 UINT64 EFER; // fed0h
146 UINT64 SVM_Guest; // fed8h
147 UINT64 SVM_GuestVMCB; // fee0h
148 UINT64 SVM_GuestVIntr; // fee8h
149 UINT8 Reserved3[0x0c]; // fef0h
150 UINT32 SMMRevId; // fefch
151 UINT32 SMBASE; // ff00h
152 UINT8 Reserved4[0x14]; // ff04h
153 UINT64 SSP; // ff18h
154 UINT64 SVM_GuestPAT; // ff20h
155 UINT64 SVM_HostEFER; // ff28h
156 UINT64 SVM_HostCR4; // ff30h
157 UINT64 SVM_HostCR3; // ff38h
158 UINT64 SVM_HostCR0; // ff40h
159 UINT64 _CR4; // ff48h
160 UINT64 _CR3; // ff50h
161 UINT64 _CR0; // ff58h
162 UINT64 _DR7; // ff60h
163 UINT64 _DR6; // ff68h
164 UINT64 _RFLAGS; // ff70h
165 UINT64 _RIP; // ff78h
166 UINT64 _R15; // ff80h
167 UINT64 _R14; // ff88h
168 UINT64 _R13; // ff90h
169 UINT64 _R12; // ff98h
170 UINT64 _R11; // ffa0h
171 UINT64 _R10; // ffa8h
172 UINT64 _R9; // ffb0h
173 UINT64 _R8; // ffb8h
174 UINT64 _RDI; // ffc0h
175 UINT64 _RSI; // ffc8h
176 UINT64 _RBP; // ffd0h
177 UINT64 _RSP; // ffd8h
178 UINT64 _RBX; // ffe0h
179 UINT64 _RDX; // ffe8h
180 UINT64 _RCX; // fff0h
181 UINT64 _RAX; // fff8h
182} AMD_SMRAM_SAVE_STATE_MAP64;
183
187typedef union {
188 AMD_SMRAM_SAVE_STATE_MAP32 x86;
189 AMD_SMRAM_SAVE_STATE_MAP64 x64;
190} AMD_SMRAM_SAVE_STATE_MAP;
191
192#pragma pack ()
193
194#endif
AMD_SMRAM_SAVE_STATE_MAP32
Definition: SmramSaveStateMap.h:35
AMD_SMRAM_SAVE_STATE_MAP64
Definition: SmramSaveStateMap.h:76
AMD_SMRAM_SAVE_STATE_MAP
Definition: SmramSaveStateMap.h:187