18#ifndef __INTEL_ARCHITECTURAL_MSR_H__
19#define __INTEL_ARCHITECTURAL_MSR_H__
37#define MSR_IA32_P5_MC_ADDR 0x00000000
55#define MSR_IA32_P5_MC_TYPE 0x00000001
74#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
93#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
114#define MSR_IA32_PLATFORM_ID 0x00000017
124 UINT32 Reserved1 : 32;
125 UINT32 Reserved2 : 18;
141 UINT32 Reserved3 : 11;
167#define MSR_IA32_APIC_BASE 0x0000001B
177 UINT32 Reserved1 : 8;
182 UINT32 Reserved2 : 1;
226#define MSR_IA32_FEATURE_CONTROL 0x0000003A
264 UINT32 Reserved1 : 5;
278 UINT32 Reserved2 : 1;
290 UINT32 Reserved3 : 1;
297 UINT32 Reserved4 : 11;
298 UINT32 Reserved5 : 32;
330#define MSR_IA32_TSC_ADJUST 0x0000003B
352#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
374#define MSR_IA32_BIOS_SIGN_ID 0x0000008B
384 UINT32 Reserved : 32;
426#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
427#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
428#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
429#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
451#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
469 UINT32 Reserved1 : 1;
475 UINT32 Reserved2 : 9;
480 UINT32 Reserved3 : 32;
512 UINT32 GdtrBaseOffset;
520 UINT8 Reserved[SIZE_2KB - 8 *
sizeof (UINT32)];
526#define STM_FEATURES_IA32E 0x1
547#define MSR_IA32_SMBASE 0x0000009E
574#define MSR_IA32_PMC0 0x000000C1
575#define MSR_IA32_PMC1 0x000000C2
576#define MSR_IA32_PMC2 0x000000C3
577#define MSR_IA32_PMC3 0x000000C4
578#define MSR_IA32_PMC4 0x000000C5
579#define MSR_IA32_PMC5 0x000000C6
580#define MSR_IA32_PMC6 0x000000C7
581#define MSR_IA32_PMC7 0x000000C8
603#define MSR_IA32_MPERF 0x000000E7
624#define MSR_IA32_APERF 0x000000E8
644#define MSR_IA32_MTRRCAP 0x000000FE
663 UINT32 Reserved1 : 1;
672 UINT32 Reserved2 : 20;
673 UINT32 Reserved3 : 32;
703#define MSR_IA32_SYSENTER_CS 0x00000174
717 UINT32 Reserved1 : 16;
718 UINT32 Reserved2 : 32;
746#define MSR_IA32_SYSENTER_ESP 0x00000175
764#define MSR_IA32_SYSENTER_EIP 0x00000176
784#define MSR_IA32_MCG_CAP 0x00000179
817 UINT32 Reserved1 : 4;
828 UINT32 Reserved2 : 1;
845 UINT32 Reserved3 : 4;
846 UINT32 Reserved4 : 32;
877#define MSR_IA32_MCG_STATUS 0x0000017A
906 UINT32 Reserved1 : 28;
907 UINT32 Reserved2 : 32;
935#define MSR_IA32_MCG_CTL 0x0000017B
959#define MSR_IA32_PERFEVTSEL0 0x00000186
960#define MSR_IA32_PERFEVTSEL1 0x00000187
961#define MSR_IA32_PERFEVTSEL2 0x00000188
962#define MSR_IA32_PERFEVTSEL3 0x00000189
1026 UINT32 Reserved : 32;
1056#define MSR_IA32_PERF_STATUS 0x00000198
1070 UINT32 Reserved1 : 16;
1071 UINT32 Reserved2 : 32;
1101#define MSR_IA32_PERF_CTL 0x00000199
1115 UINT32 Reserved1 : 16;
1121 UINT32 Reserved2 : 31;
1148#define MSR_IA32_CLOCK_MODULATION 0x0000019A
1173 UINT32 Reserved1 : 27;
1174 UINT32 Reserved2 : 32;
1207#define MSR_IA32_THERM_INTERRUPT 0x0000019B
1238 UINT32 Reserved1 : 3;
1259 UINT32 Reserved2 : 7;
1260 UINT32 Reserved3 : 32;
1291#define MSR_IA32_THERM_STATUS 0x0000019C
1370 UINT32 Reserved1 : 4;
1380 UINT32 Reserved2 : 32;
1411#define MSR_IA32_MISC_ENABLE 0x000001A0
1427 UINT32 Reserved1 : 2;
1440 UINT32 Reserved2 : 3;
1447 UINT32 Reserved3 : 3;
1460 UINT32 Reserved4 : 3;
1467 UINT32 Reserved5 : 1;
1481 UINT32 Reserved6 : 3;
1502 UINT32 Reserved7 : 8;
1503 UINT32 Reserved8 : 2;
1515 UINT32 Reserved9 : 29;
1541#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
1556 UINT32 Reserved1 : 28;
1557 UINT32 Reserved2 : 32;
1588#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
1646 UINT32 Reserved1 : 4;
1651 UINT32 Reserved2 : 9;
1652 UINT32 Reserved3 : 32;
1685#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
1707 UINT32 Reserved1 : 1;
1712 UINT32 Reserved2 : 3;
1733 UINT32 Reserved3 : 7;
1734 UINT32 Reserved4 : 32;
1765#define MSR_IA32_DEBUGCTL 0x000001D9
1787 UINT32 Reserved1 : 4;
1843 UINT32 Reserved2 : 16;
1844 UINT32 Reserved3 : 32;
1875#define MSR_IA32_SMRR_PHYSBASE 0x000001F2
1889 UINT32 Reserved1 : 4;
1894 UINT32 Reserved2 : 32;
1925#define MSR_IA32_SMRR_PHYSMASK 0x000001F3
1935 UINT32 Reserved1 : 11;
1944 UINT32 Reserved2 : 32;
1971#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
1989#define MSR_IA32_CPU_DCA_CAP 0x000001F9
2009#define MSR_IA32_DCA_0_CAP 0x000001FA
2036 UINT32 Reserved1 : 2;
2042 UINT32 Reserved2 : 7;
2047 UINT32 Reserved3 : 1;
2052 UINT32 Reserved4 : 5;
2053 UINT32 Reserved5 : 32;
2094#define MSR_IA32_MTRR_PHYSBASE0 0x00000200
2095#define MSR_IA32_MTRR_PHYSBASE1 0x00000202
2096#define MSR_IA32_MTRR_PHYSBASE2 0x00000204
2097#define MSR_IA32_MTRR_PHYSBASE3 0x00000206
2098#define MSR_IA32_MTRR_PHYSBASE4 0x00000208
2099#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
2100#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
2101#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
2102#define MSR_IA32_MTRR_PHYSBASE8 0x00000210
2103#define MSR_IA32_MTRR_PHYSBASE9 0x00000212
2106#define MSR_IA32_MTRR_CACHE_UNCACHEABLE 0
2107#define MSR_IA32_MTRR_CACHE_WRITE_COMBINING 1
2108#define MSR_IA32_MTRR_CACHE_WRITE_THROUGH 4
2109#define MSR_IA32_MTRR_CACHE_WRITE_PROTECTED 5
2110#define MSR_IA32_MTRR_CACHE_WRITE_BACK 6
2111#define MSR_IA32_MTRR_CACHE_INVALID_TYPE 7
2126 UINT32 Reserved1 : 4;
2176#define MSR_IA32_MTRR_PHYSMASK0 0x00000201
2177#define MSR_IA32_MTRR_PHYSMASK1 0x00000203
2178#define MSR_IA32_MTRR_PHYSMASK2 0x00000205
2179#define MSR_IA32_MTRR_PHYSMASK3 0x00000207
2180#define MSR_IA32_MTRR_PHYSMASK4 0x00000209
2181#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
2182#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
2183#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
2184#define MSR_IA32_MTRR_PHYSMASK8 0x00000211
2185#define MSR_IA32_MTRR_PHYSMASK9 0x00000213
2197 UINT32 Reserved1 : 11;
2238#define MSR_IA32_MTRR_FIX64K_00000 0x00000250
2256#define MSR_IA32_MTRR_FIX16K_80000 0x00000258
2274#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
2292#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
2310#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
2328#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
2346#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
2364#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
2382#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
2400#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
2418#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
2438#define MSR_IA32_PAT 0x00000277
2452 UINT32 Reserved1 : 5;
2457 UINT32 Reserved2 : 5;
2462 UINT32 Reserved3 : 5;
2467 UINT32 Reserved4 : 5;
2472 UINT32 Reserved5 : 5;
2477 UINT32 Reserved6 : 5;
2482 UINT32 Reserved7 : 5;
2487 UINT32 Reserved8 : 5;
2546#define MSR_IA32_MC0_CTL2 0x00000280
2547#define MSR_IA32_MC1_CTL2 0x00000281
2548#define MSR_IA32_MC2_CTL2 0x00000282
2549#define MSR_IA32_MC3_CTL2 0x00000283
2550#define MSR_IA32_MC4_CTL2 0x00000284
2551#define MSR_IA32_MC5_CTL2 0x00000285
2552#define MSR_IA32_MC6_CTL2 0x00000286
2553#define MSR_IA32_MC7_CTL2 0x00000287
2554#define MSR_IA32_MC8_CTL2 0x00000288
2555#define MSR_IA32_MC9_CTL2 0x00000289
2556#define MSR_IA32_MC10_CTL2 0x0000028A
2557#define MSR_IA32_MC11_CTL2 0x0000028B
2558#define MSR_IA32_MC12_CTL2 0x0000028C
2559#define MSR_IA32_MC13_CTL2 0x0000028D
2560#define MSR_IA32_MC14_CTL2 0x0000028E
2561#define MSR_IA32_MC15_CTL2 0x0000028F
2562#define MSR_IA32_MC16_CTL2 0x00000290
2563#define MSR_IA32_MC17_CTL2 0x00000291
2564#define MSR_IA32_MC18_CTL2 0x00000292
2565#define MSR_IA32_MC19_CTL2 0x00000293
2566#define MSR_IA32_MC20_CTL2 0x00000294
2567#define MSR_IA32_MC21_CTL2 0x00000295
2568#define MSR_IA32_MC22_CTL2 0x00000296
2569#define MSR_IA32_MC23_CTL2 0x00000297
2570#define MSR_IA32_MC24_CTL2 0x00000298
2571#define MSR_IA32_MC25_CTL2 0x00000299
2572#define MSR_IA32_MC26_CTL2 0x0000029A
2573#define MSR_IA32_MC27_CTL2 0x0000029B
2574#define MSR_IA32_MC28_CTL2 0x0000029C
2575#define MSR_IA32_MC29_CTL2 0x0000029D
2576#define MSR_IA32_MC30_CTL2 0x0000029E
2577#define MSR_IA32_MC31_CTL2 0x0000029F
2593 UINT32 Reserved1 : 15;
2598 UINT32 Reserved2 : 1;
2599 UINT32 Reserved3 : 32;
2629#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
2643 UINT32 Reserved1 : 7;
2652 UINT32 Reserved2 : 20;
2653 UINT32 Reserved3 : 32;
2682#define MSR_IA32_FIXED_CTR0 0x00000309
2701#define MSR_IA32_FIXED_CTR1 0x0000030A
2720#define MSR_IA32_FIXED_CTR2 0x0000030B
2740#define MSR_IA32_PERF_CAPABILITIES 0x00000345
2774 UINT32 Reserved1 : 18;
2775 UINT32 Reserved2 : 32;
2808#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
2878 UINT32 Reserved1 : 20;
2879 UINT32 Reserved2 : 32;
2908#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
2938 UINT32 Reserved1 : 28;
2954 UINT32 Reserved2 : 20;
2961 UINT32 Reserved3 : 2;
3023#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
3071#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
3099 UINT32 Reserved2 : 5;
3139#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
3167 UINT32 Reserved2 : 2;
3219#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
3246 UINT32 Reserved2 : 2;
3267 UINT32 Reserved3 : 1;
3293#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
3345#define MSR_IA32_PEBS_ENABLE 0x000003F1
3364 UINT32 Reserved2 : 28;
3369 UINT32 Reserved4 : 28;
3422#define MSR_IA32_MC0_CTL 0x00000400
3423#define MSR_IA32_MC1_CTL 0x00000404
3424#define MSR_IA32_MC2_CTL 0x00000408
3425#define MSR_IA32_MC3_CTL 0x0000040C
3426#define MSR_IA32_MC4_CTL 0x00000410
3427#define MSR_IA32_MC5_CTL 0x00000414
3428#define MSR_IA32_MC6_CTL 0x00000418
3429#define MSR_IA32_MC7_CTL 0x0000041C
3430#define MSR_IA32_MC8_CTL 0x00000420
3431#define MSR_IA32_MC9_CTL 0x00000424
3432#define MSR_IA32_MC10_CTL 0x00000428
3433#define MSR_IA32_MC11_CTL 0x0000042C
3434#define MSR_IA32_MC12_CTL 0x00000430
3435#define MSR_IA32_MC13_CTL 0x00000434
3436#define MSR_IA32_MC14_CTL 0x00000438
3437#define MSR_IA32_MC15_CTL 0x0000043C
3438#define MSR_IA32_MC16_CTL 0x00000440
3439#define MSR_IA32_MC17_CTL 0x00000444
3440#define MSR_IA32_MC18_CTL 0x00000448
3441#define MSR_IA32_MC19_CTL 0x0000044C
3442#define MSR_IA32_MC20_CTL 0x00000450
3443#define MSR_IA32_MC21_CTL 0x00000454
3444#define MSR_IA32_MC22_CTL 0x00000458
3445#define MSR_IA32_MC23_CTL 0x0000045C
3446#define MSR_IA32_MC24_CTL 0x00000460
3447#define MSR_IA32_MC25_CTL 0x00000464
3448#define MSR_IA32_MC26_CTL 0x00000468
3449#define MSR_IA32_MC27_CTL 0x0000046C
3450#define MSR_IA32_MC28_CTL 0x00000470
3498#define MSR_IA32_MC0_STATUS 0x00000401
3499#define MSR_IA32_MC1_STATUS 0x00000405
3500#define MSR_IA32_MC2_STATUS 0x00000409
3501#define MSR_IA32_MC3_STATUS 0x0000040D
3502#define MSR_IA32_MC4_STATUS 0x00000411
3503#define MSR_IA32_MC5_STATUS 0x00000415
3504#define MSR_IA32_MC6_STATUS 0x00000419
3505#define MSR_IA32_MC7_STATUS 0x0000041D
3506#define MSR_IA32_MC8_STATUS 0x00000421
3507#define MSR_IA32_MC9_STATUS 0x00000425
3508#define MSR_IA32_MC10_STATUS 0x00000429
3509#define MSR_IA32_MC11_STATUS 0x0000042D
3510#define MSR_IA32_MC12_STATUS 0x00000431
3511#define MSR_IA32_MC13_STATUS 0x00000435
3512#define MSR_IA32_MC14_STATUS 0x00000439
3513#define MSR_IA32_MC15_STATUS 0x0000043D
3514#define MSR_IA32_MC16_STATUS 0x00000441
3515#define MSR_IA32_MC17_STATUS 0x00000445
3516#define MSR_IA32_MC18_STATUS 0x00000449
3517#define MSR_IA32_MC19_STATUS 0x0000044D
3518#define MSR_IA32_MC20_STATUS 0x00000451
3519#define MSR_IA32_MC21_STATUS 0x00000455
3520#define MSR_IA32_MC22_STATUS 0x00000459
3521#define MSR_IA32_MC23_STATUS 0x0000045D
3522#define MSR_IA32_MC24_STATUS 0x00000461
3523#define MSR_IA32_MC25_STATUS 0x00000465
3524#define MSR_IA32_MC26_STATUS 0x00000469
3525#define MSR_IA32_MC27_STATUS 0x0000046D
3526#define MSR_IA32_MC28_STATUS 0x00000471
3574#define MSR_IA32_MC0_ADDR 0x00000402
3575#define MSR_IA32_MC1_ADDR 0x00000406
3576#define MSR_IA32_MC2_ADDR 0x0000040A
3577#define MSR_IA32_MC3_ADDR 0x0000040E
3578#define MSR_IA32_MC4_ADDR 0x00000412
3579#define MSR_IA32_MC5_ADDR 0x00000416
3580#define MSR_IA32_MC6_ADDR 0x0000041A
3581#define MSR_IA32_MC7_ADDR 0x0000041E
3582#define MSR_IA32_MC8_ADDR 0x00000422
3583#define MSR_IA32_MC9_ADDR 0x00000426
3584#define MSR_IA32_MC10_ADDR 0x0000042A
3585#define MSR_IA32_MC11_ADDR 0x0000042E
3586#define MSR_IA32_MC12_ADDR 0x00000432
3587#define MSR_IA32_MC13_ADDR 0x00000436
3588#define MSR_IA32_MC14_ADDR 0x0000043A
3589#define MSR_IA32_MC15_ADDR 0x0000043E
3590#define MSR_IA32_MC16_ADDR 0x00000442
3591#define MSR_IA32_MC17_ADDR 0x00000446
3592#define MSR_IA32_MC18_ADDR 0x0000044A
3593#define MSR_IA32_MC19_ADDR 0x0000044E
3594#define MSR_IA32_MC20_ADDR 0x00000452
3595#define MSR_IA32_MC21_ADDR 0x00000456
3596#define MSR_IA32_MC22_ADDR 0x0000045A
3597#define MSR_IA32_MC23_ADDR 0x0000045E
3598#define MSR_IA32_MC24_ADDR 0x00000462
3599#define MSR_IA32_MC25_ADDR 0x00000466
3600#define MSR_IA32_MC26_ADDR 0x0000046A
3601#define MSR_IA32_MC27_ADDR 0x0000046E
3602#define MSR_IA32_MC28_ADDR 0x00000472
3650#define MSR_IA32_MC0_MISC 0x00000403
3651#define MSR_IA32_MC1_MISC 0x00000407
3652#define MSR_IA32_MC2_MISC 0x0000040B
3653#define MSR_IA32_MC3_MISC 0x0000040F
3654#define MSR_IA32_MC4_MISC 0x00000413
3655#define MSR_IA32_MC5_MISC 0x00000417
3656#define MSR_IA32_MC6_MISC 0x0000041B
3657#define MSR_IA32_MC7_MISC 0x0000041F
3658#define MSR_IA32_MC8_MISC 0x00000423
3659#define MSR_IA32_MC9_MISC 0x00000427
3660#define MSR_IA32_MC10_MISC 0x0000042B
3661#define MSR_IA32_MC11_MISC 0x0000042F
3662#define MSR_IA32_MC12_MISC 0x00000433
3663#define MSR_IA32_MC13_MISC 0x00000437
3664#define MSR_IA32_MC14_MISC 0x0000043B
3665#define MSR_IA32_MC15_MISC 0x0000043F
3666#define MSR_IA32_MC16_MISC 0x00000443
3667#define MSR_IA32_MC17_MISC 0x00000447
3668#define MSR_IA32_MC18_MISC 0x0000044B
3669#define MSR_IA32_MC19_MISC 0x0000044F
3670#define MSR_IA32_MC20_MISC 0x00000453
3671#define MSR_IA32_MC21_MISC 0x00000457
3672#define MSR_IA32_MC22_MISC 0x0000045B
3673#define MSR_IA32_MC23_MISC 0x0000045F
3674#define MSR_IA32_MC24_MISC 0x00000463
3675#define MSR_IA32_MC25_MISC 0x00000467
3676#define MSR_IA32_MC26_MISC 0x0000046B
3677#define MSR_IA32_MC27_MISC 0x0000046F
3678#define MSR_IA32_MC28_MISC 0x00000473
3697#define MSR_IA32_VMX_BASIC 0x00000480
3718 UINT32 MustBeZero : 1;
3725 UINT32 Reserved1 : 3;
3787 UINT32 Reserved2 : 8;
3798#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00
3799#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06
3820#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
3839#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
3857#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
3875#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
3893#define MSR_IA32_VMX_MISC 0x00000485
3929 UINT32 Reserved1 : 5;
3980 UINT32 Reserved2 : 1;
4009#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
4027#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
4045#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
4063#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
4081#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
4100#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
4119#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
4138#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
4157#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
4175#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
4193#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
4211#define MSR_IA32_VMX_VMFUNC 0x00000491
4238#define MSR_IA32_A_PMC0 0x000004C1
4239#define MSR_IA32_A_PMC1 0x000004C2
4240#define MSR_IA32_A_PMC2 0x000004C3
4241#define MSR_IA32_A_PMC3 0x000004C4
4242#define MSR_IA32_A_PMC4 0x000004C5
4243#define MSR_IA32_A_PMC5 0x000004C6
4244#define MSR_IA32_A_PMC6 0x000004C7
4245#define MSR_IA32_A_PMC7 0x000004C8
4266#define MSR_IA32_MCG_EXT_CTL 0x000004D0
4280 UINT32 Reserved1 : 31;
4281 UINT32 Reserved2 : 32;
4311#define MSR_IA32_SGX_SVN_STATUS 0x00000500
4326 UINT32 Reserved1 : 15;
4332 UINT32 Reserved2 : 8;
4333 UINT32 Reserved3 : 32;
4365#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
4375 UINT32 Reserved : 7;
4411#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
4421 UINT32 Reserved : 7;
4449 UINT32 Reserved1 : 1;
4454 UINT32 Reserved2 : 1;
4459 UINT32 Reserved3 : 1;
4465 UINT32 Reserved4 : 2;
4497 RtitTopaMemorySize4K = 0,
4498 RtitTopaMemorySize8K,
4499 RtitTopaMemorySize16K,
4500 RtitTopaMemorySize32K,
4501 RtitTopaMemorySize64K,
4502 RtitTopaMemorySize128K,
4503 RtitTopaMemorySize256K,
4504 RtitTopaMemorySize512K,
4505 RtitTopaMemorySize1M,
4506 RtitTopaMemorySize2M,
4507 RtitTopaMemorySize4M,
4508 RtitTopaMemorySize8M,
4509 RtitTopaMemorySize16M,
4510 RtitTopaMemorySize32M,
4511 RtitTopaMemorySize64M,
4512 RtitTopaMemorySize128M
4533#define MSR_IA32_RTIT_CTL 0x00000570
4603 UINT32 Reserved3 : 1;
4608 UINT32 Reserved4 : 1;
4613 UINT32 Reserved5 : 4;
4630 UINT32 Reserved6 : 16;
4656#define MSR_IA32_RTIT_STATUS 0x00000571
4679 UINT32 Reserved1 : 1;
4688 UINT32 Reserved2 : 26;
4693 UINT32 Reserved3 : 15;
4720#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
4730 UINT32 Reserved : 5;
4768#define MSR_IA32_RTIT_ADDR0_A 0x00000580
4769#define MSR_IA32_RTIT_ADDR1_A 0x00000582
4770#define MSR_IA32_RTIT_ADDR2_A 0x00000584
4771#define MSR_IA32_RTIT_ADDR3_A 0x00000586
4796#define MSR_IA32_RTIT_ADDR0_B 0x00000581
4797#define MSR_IA32_RTIT_ADDR1_B 0x00000583
4798#define MSR_IA32_RTIT_ADDR2_B 0x00000585
4799#define MSR_IA32_RTIT_ADDR3_B 0x00000587
4853#define MSR_IA32_DS_AREA 0x00000600
4872#define MSR_IA32_TSC_DEADLINE 0x000006E0
4892#define MSR_IA32_PM_ENABLE 0x00000770
4907 UINT32 Reserved1 : 31;
4908 UINT32 Reserved2 : 32;
4937#define MSR_IA32_HWP_CAPABILITIES 0x00000771
4967 UINT32 Reserved : 32;
4998#define MSR_IA32_HWP_REQUEST_PKG 0x00000772
5033 UINT32 Reserved : 22;
5059#define MSR_IA32_HWP_INTERRUPT 0x00000773
5079 UINT32 Reserved1 : 30;
5080 UINT32 Reserved2 : 32;
5111#define MSR_IA32_HWP_REQUEST 0x00000774
5151 UINT32 Reserved : 21;
5178#define MSR_IA32_HWP_STATUS 0x00000777
5193 UINT32 Reserved1 : 1;
5199 UINT32 Reserved2 : 29;
5200 UINT32 Reserved3 : 32;
5228#define MSR_IA32_X2APIC_APICID 0x00000802
5246#define MSR_IA32_X2APIC_VERSION 0x00000803
5265#define MSR_IA32_X2APIC_TPR 0x00000808
5283#define MSR_IA32_X2APIC_PPR 0x0000080A
5302#define MSR_IA32_X2APIC_EOI 0x0000080B
5320#define MSR_IA32_X2APIC_LDR 0x0000080D
5339#define MSR_IA32_X2APIC_SIVR 0x0000080F
5365#define MSR_IA32_X2APIC_ISR0 0x00000810
5366#define MSR_IA32_X2APIC_ISR1 0x00000811
5367#define MSR_IA32_X2APIC_ISR2 0x00000812
5368#define MSR_IA32_X2APIC_ISR3 0x00000813
5369#define MSR_IA32_X2APIC_ISR4 0x00000814
5370#define MSR_IA32_X2APIC_ISR5 0x00000815
5371#define MSR_IA32_X2APIC_ISR6 0x00000816
5372#define MSR_IA32_X2APIC_ISR7 0x00000817
5399#define MSR_IA32_X2APIC_TMR0 0x00000818
5400#define MSR_IA32_X2APIC_TMR1 0x00000819
5401#define MSR_IA32_X2APIC_TMR2 0x0000081A
5402#define MSR_IA32_X2APIC_TMR3 0x0000081B
5403#define MSR_IA32_X2APIC_TMR4 0x0000081C
5404#define MSR_IA32_X2APIC_TMR5 0x0000081D
5405#define MSR_IA32_X2APIC_TMR6 0x0000081E
5406#define MSR_IA32_X2APIC_TMR7 0x0000081F
5433#define MSR_IA32_X2APIC_IRR0 0x00000820
5434#define MSR_IA32_X2APIC_IRR1 0x00000821
5435#define MSR_IA32_X2APIC_IRR2 0x00000822
5436#define MSR_IA32_X2APIC_IRR3 0x00000823
5437#define MSR_IA32_X2APIC_IRR4 0x00000824
5438#define MSR_IA32_X2APIC_IRR5 0x00000825
5439#define MSR_IA32_X2APIC_IRR6 0x00000826
5440#define MSR_IA32_X2APIC_IRR7 0x00000827
5460#define MSR_IA32_X2APIC_ESR 0x00000828
5479#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
5498#define MSR_IA32_X2APIC_ICR 0x00000830
5517#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
5536#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
5555#define MSR_IA32_X2APIC_LVT_PMI 0x00000834
5574#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
5593#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
5612#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
5631#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
5649#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
5668#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
5687#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
5707#define MSR_IA32_TME_ACTIVATE 0x00000982
5749 UINT32 Reserved : 23;
5771 UINT32 Reserved2 : 12;
5811#define MSR_IA32_DEBUG_INTERFACE 0x00000C80
5826 UINT32 Reserved1 : 29;
5838 UINT32 Reserved2 : 32;
5868#define MSR_IA32_L3_QOS_CFG 0x00000C81
5883 UINT32 Reserved1 : 31;
5884 UINT32 Reserved2 : 32;
5914#define MSR_IA32_L2_QOS_CFG 0x00000C82
5929 UINT32 Reserved1 : 31;
5930 UINT32 Reserved2 : 32;
5961#define MSR_IA32_QM_EVTSEL 0x00000C8D
5976 UINT32 Reserved : 24;
6008#define MSR_IA32_QM_CTR 0x00000C8E
6062#define MSR_IA32_PQR_ASSOC 0x00000C8F
6110#define MSR_IA32_BNDCFGS 0x00000D90
6129 UINT32 Reserved : 10;
6163#define MSR_IA32_XSS 0x00000DA0
6173 UINT32 Reserved1 : 8;
6178 UINT32 Reserved2 : 23;
6179 UINT32 Reserved3 : 32;
6209#define MSR_IA32_PKG_HDC_CTL 0x00000DB0
6225 UINT32 Reserved1 : 31;
6226 UINT32 Reserved2 : 32;
6256#define MSR_IA32_PM_CTL1 0x00000DB1
6272 UINT32 Reserved1 : 31;
6273 UINT32 Reserved2 : 32;
6302#define MSR_IA32_THREAD_STALL 0x00000DB2
6323#define MSR_IA32_EFER 0xC0000080
6338 UINT32 Reserved1 : 7;
6344 UINT32 Reserved2 : 1;
6354 UINT32 Reserved3 : 20;
6355 UINT32 Reserved4 : 32;
6383#define MSR_IA32_STAR 0xC0000081
6401#define MSR_IA32_LSTAR 0xC0000082
6421#define MSR_IA32_CSTAR 0xC0000083
6439#define MSR_IA32_FMASK 0xC0000084
6457#define MSR_IA32_FS_BASE 0xC0000100
6475#define MSR_IA32_GS_BASE 0xC0000101
6493#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
6513#define MSR_IA32_TSC_AUX 0xC0000103
6527 UINT32 Reserved : 32;
UINT32 MsegHeaderRevision
UINT32 MsrStoreListMaximum
UINT32 HltActivityStateSupported
UINT32 WaitForSipiActivityStateSupported
UINT32 NumberOfCr3TargetValues
UINT32 ShutdownActivityStateSupported
UINT32 SmBaseMsrSupported
UINT32 ProcessorTraceSupported
UINT32 MsegRevisionIdentifier
UINT32 MicrocodeUpdateSignature
UINT32 OnDemandClockModulationDutyCycle
UINT32 ExtendedOnDemandClockModulationDutyCycle
UINT32 OnDemandClockModulationEnable
UINT32 FREEZE_PERFMON_ON_PMI
UINT32 FREEZE_LBRS_ON_PMI
UINT32 PowerPolicyPreference
UINT32 SgxLaunchControlEnable
UINT32 EnableVmxInsideSmx
UINT32 EnableVmxOutsideSmx
UINT32 SenterGlobalEnable
UINT32 SenterLocalFunctionEnables
UINT32 Lowest_Performance
UINT32 Highest_Performance
UINT32 Most_Efficient_Performance
UINT32 Guaranteed_Performance
UINT32 EN_Excursion_Minimum
UINT32 EN_Guaranteed_Performance_Change
UINT32 Desired_Performance
UINT32 Energy_Performance_Preference
UINT32 Maximum_Performance
UINT32 Minimum_Performance
UINT32 Minimum_Performance
UINT32 Energy_Performance_Preference
UINT32 Desired_Performance
UINT32 Maximum_Performance
UINT32 Guaranteed_Performance_Change
UINT32 Excursion_To_Minimum
UINT32 CorrectedErrorCountThreshold
UINT32 AutomaticThermalControlCircuit
UINT32 xTPR_Message_Disable
UINT32 PerformanceMonitoring
UINT32 PowerLimitNotificationEnable
UINT32 CriticalTempStatus
UINT32 CriticalTempStatusLog
UINT32 ThermalThreshold2Log
UINT32 ThermalThreshold1Log
UINT32 ThermalThreshold1Status
UINT32 ThermalThreshold2Status
UINT32 ResourceMonitoringID
UINT32 ResourceMonitoredData
UINT32 ResourceMonitoredDataHi
UINT32 ResourceMonitoringID
UINT32 PowerLimitNotificationEnable
UINT32 CriticalTempEnable
UINT32 PROCHOT_FORCEPR_Log
UINT32 CriticalTempStatusLog
UINT32 ThermalThreshold2Log
UINT32 CrossDomainLimitLog
UINT32 ThermalThreshold1Log
UINT32 CurrentLimitStatus
UINT32 ResolutionInDegreesCelsius
UINT32 ThermalThreshold1Status
UINT32 CrossDomainLimitStatus
UINT32 CriticalTempStatus
UINT32 ThermalThreshold2Status
UINT32 PROCHOT_FORCEPR_Event
UINT32 TracePacketConfigurationState