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ArchitecturalMsr.h
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1
18#ifndef __INTEL_ARCHITECTURAL_MSR_H__
19#define __INTEL_ARCHITECTURAL_MSR_H__
20
37#define MSR_IA32_P5_MC_ADDR 0x00000000
38
55#define MSR_IA32_P5_MC_TYPE 0x00000001
56
74#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
75
93#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
94
114#define MSR_IA32_PLATFORM_ID 0x00000017
115
119typedef union {
123 struct {
124 UINT32 Reserved1 : 32;
125 UINT32 Reserved2 : 18;
140 UINT32 PlatformId : 3;
141 UINT32 Reserved3 : 11;
142 } Bits;
146 UINT64 Uint64;
148
167#define MSR_IA32_APIC_BASE 0x0000001B
168
172typedef union {
176 struct {
177 UINT32 Reserved1 : 8;
181 UINT32 BSP : 1;
182 UINT32 Reserved2 : 1;
187 UINT32 EXTD : 1;
191 UINT32 EN : 1;
195 UINT32 ApicBase : 20;
199 UINT32 ApicBaseHi : 32;
200 } Bits;
204 UINT64 Uint64;
206
226#define MSR_IA32_FEATURE_CONTROL 0x0000003A
227
231typedef union {
235 struct {
247 UINT32 Lock : 1;
264 UINT32 Reserved1 : 5;
278 UINT32 Reserved2 : 1;
289 UINT32 SgxEnable : 1;
290 UINT32 Reserved3 : 1;
296 UINT32 LmceOn : 1;
297 UINT32 Reserved4 : 11;
298 UINT32 Reserved5 : 32;
299 } Bits;
303 UINT32 Uint32;
307 UINT64 Uint64;
309
330#define MSR_IA32_TSC_ADJUST 0x0000003B
331
352#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
353
374#define MSR_IA32_BIOS_SIGN_ID 0x0000008B
375
379typedef union {
383 struct {
384 UINT32 Reserved : 32;
395 } Bits;
399 UINT64 Uint64;
401
426#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
427#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
428#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
429#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
431
451#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
452
456typedef union {
460 struct {
468 UINT32 Valid : 1;
469 UINT32 Reserved1 : 1;
474 UINT32 BlockSmi : 1;
475 UINT32 Reserved2 : 9;
479 UINT32 MsegBase : 20;
480 UINT32 Reserved3 : 32;
481 } Bits;
485 UINT32 Uint32;
489 UINT64 Uint64;
491
496typedef struct {
503 //
511 UINT32 GdtrLimit;
512 UINT32 GdtrBaseOffset;
513 UINT32 CsSelector;
514 UINT32 EipOffset;
515 UINT32 EspOffset;
516 UINT32 Cr3Offset;
520 UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
522
526#define STM_FEATURES_IA32E 0x1
530
547#define MSR_IA32_SMBASE 0x0000009E
548
574#define MSR_IA32_PMC0 0x000000C1
575#define MSR_IA32_PMC1 0x000000C2
576#define MSR_IA32_PMC2 0x000000C3
577#define MSR_IA32_PMC3 0x000000C4
578#define MSR_IA32_PMC4 0x000000C5
579#define MSR_IA32_PMC5 0x000000C6
580#define MSR_IA32_PMC6 0x000000C7
581#define MSR_IA32_PMC7 0x000000C8
583
603#define MSR_IA32_MPERF 0x000000E7
604
624#define MSR_IA32_APERF 0x000000E8
625
644#define MSR_IA32_MTRRCAP 0x000000FE
645
649typedef union {
653 struct {
658 UINT32 VCNT : 8;
662 UINT32 FIX : 1;
663 UINT32 Reserved1 : 1;
667 UINT32 WC : 1;
671 UINT32 SMRR : 1;
672 UINT32 Reserved2 : 20;
673 UINT32 Reserved3 : 32;
674 } Bits;
678 UINT32 Uint32;
682 UINT64 Uint64;
684
703#define MSR_IA32_SYSENTER_CS 0x00000174
704
708typedef union {
712 struct {
716 UINT32 CS : 16;
717 UINT32 Reserved1 : 16;
718 UINT32 Reserved2 : 32;
719 } Bits;
723 UINT32 Uint32;
727 UINT64 Uint64;
729
746#define MSR_IA32_SYSENTER_ESP 0x00000175
747
764#define MSR_IA32_SYSENTER_EIP 0x00000176
765
784#define MSR_IA32_MCG_CAP 0x00000179
785
789typedef union {
793 struct {
797 UINT32 Count : 8;
801 UINT32 MCG_CTL_P : 1;
806 UINT32 MCG_EXT_P : 1;
811 UINT32 MCP_CMCI_P : 1;
816 UINT32 MCG_TES_P : 1;
817 UINT32 Reserved1 : 4;
822 UINT32 MCG_EXT_CNT : 8;
827 UINT32 MCG_SER_P : 1;
828 UINT32 Reserved2 : 1;
837 UINT32 MCG_ELOG_P : 1;
844 UINT32 MCG_LMCE_P : 1;
845 UINT32 Reserved3 : 4;
846 UINT32 Reserved4 : 32;
847 } Bits;
851 UINT32 Uint32;
855 UINT64 Uint64;
857
877#define MSR_IA32_MCG_STATUS 0x0000017A
878
882typedef union {
886 struct {
891 UINT32 RIPV : 1;
896 UINT32 EIPV : 1;
901 UINT32 MCIP : 1;
905 UINT32 LMCE_S : 1;
906 UINT32 Reserved1 : 28;
907 UINT32 Reserved2 : 32;
908 } Bits;
912 UINT32 Uint32;
916 UINT64 Uint64;
918
935#define MSR_IA32_MCG_CTL 0x0000017B
936
959#define MSR_IA32_PERFEVTSEL0 0x00000186
960#define MSR_IA32_PERFEVTSEL1 0x00000187
961#define MSR_IA32_PERFEVTSEL2 0x00000188
962#define MSR_IA32_PERFEVTSEL3 0x00000189
964
969typedef union {
973 struct {
977 UINT32 EventSelect : 8;
982 UINT32 UMASK : 8;
986 UINT32 USR : 1;
990 UINT32 OS : 1;
994 UINT32 E : 1;
998 UINT32 PC : 1;
1002 UINT32 INT : 1;
1010 UINT32 ANY : 1;
1015 UINT32 EN : 1;
1019 UINT32 INV : 1;
1025 UINT32 CMASK : 8;
1026 UINT32 Reserved : 32;
1027 } Bits;
1031 UINT32 Uint32;
1035 UINT64 Uint64;
1037
1056#define MSR_IA32_PERF_STATUS 0x00000198
1057
1061typedef union {
1065 struct {
1069 UINT32 State : 16;
1070 UINT32 Reserved1 : 16;
1071 UINT32 Reserved2 : 32;
1072 } Bits;
1076 UINT32 Uint32;
1080 UINT64 Uint64;
1082
1101#define MSR_IA32_PERF_CTL 0x00000199
1102
1106typedef union {
1110 struct {
1114 UINT32 TargetState : 16;
1115 UINT32 Reserved1 : 16;
1120 UINT32 IDA : 1;
1121 UINT32 Reserved2 : 31;
1122 } Bits;
1126 UINT64 Uint64;
1128
1148#define MSR_IA32_CLOCK_MODULATION 0x0000019A
1149
1153typedef union {
1157 struct {
1173 UINT32 Reserved1 : 27;
1174 UINT32 Reserved2 : 32;
1175 } Bits;
1179 UINT32 Uint32;
1183 UINT64 Uint64;
1185
1207#define MSR_IA32_THERM_INTERRUPT 0x0000019B
1208
1212typedef union {
1216 struct {
1220 UINT32 HighTempEnable : 1;
1224 UINT32 LowTempEnable : 1;
1228 UINT32 PROCHOT_Enable : 1;
1232 UINT32 FORCEPR_Enable : 1;
1238 UINT32 Reserved1 : 3;
1242 UINT32 Threshold1 : 7;
1250 UINT32 Threshold2 : 7;
1259 UINT32 Reserved2 : 7;
1260 UINT32 Reserved3 : 32;
1261 } Bits;
1265 UINT32 Uint32;
1269 UINT64 Uint64;
1271
1291#define MSR_IA32_THERM_STATUS 0x0000019C
1292
1296typedef union {
1300 struct {
1304 UINT32 ThermalStatus : 1;
1349 UINT32 PowerLimitLog : 1;
1369 UINT32 DigitalReadout : 7;
1370 UINT32 Reserved1 : 4;
1379 UINT32 ReadingValid : 1;
1380 UINT32 Reserved2 : 32;
1381 } Bits;
1385 UINT32 Uint32;
1389 UINT64 Uint64;
1391
1411#define MSR_IA32_MISC_ENABLE 0x000001A0
1412
1416typedef union {
1420 struct {
1426 UINT32 FastStrings : 1;
1427 UINT32 Reserved1 : 2;
1440 UINT32 Reserved2 : 3;
1447 UINT32 Reserved3 : 3;
1453 UINT32 BTS : 1;
1459 UINT32 PEBS : 1;
1460 UINT32 Reserved4 : 3;
1466 UINT32 EIST : 1;
1467 UINT32 Reserved5 : 1;
1480 UINT32 MONITOR : 1;
1481 UINT32 Reserved6 : 3;
1502 UINT32 Reserved7 : 8;
1503 UINT32 Reserved8 : 2;
1514 UINT32 XD : 1;
1515 UINT32 Reserved9 : 29;
1516 } Bits;
1520 UINT64 Uint64;
1522
1541#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
1542
1546typedef union {
1550 struct {
1556 UINT32 Reserved1 : 28;
1557 UINT32 Reserved2 : 32;
1558 } Bits;
1562 UINT32 Uint32;
1566 UINT64 Uint64;
1568
1588#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
1589
1593typedef union {
1597 struct {
1601 UINT32 ThermalStatus : 1;
1609 UINT32 PROCHOT_Event : 1;
1613 UINT32 PROCHOT_Log : 1;
1645 UINT32 PowerLimitLog : 1;
1646 UINT32 Reserved1 : 4;
1650 UINT32 DigitalReadout : 7;
1651 UINT32 Reserved2 : 9;
1652 UINT32 Reserved3 : 32;
1653 } Bits;
1657 UINT32 Uint32;
1661 UINT64 Uint64;
1663
1685#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
1686
1690typedef union {
1694 struct {
1698 UINT32 HighTempEnable : 1;
1702 UINT32 LowTempEnable : 1;
1706 UINT32 PROCHOT_Enable : 1;
1707 UINT32 Reserved1 : 1;
1711 UINT32 OverheatEnable : 1;
1712 UINT32 Reserved2 : 3;
1716 UINT32 Threshold1 : 7;
1724 UINT32 Threshold2 : 7;
1733 UINT32 Reserved3 : 7;
1734 UINT32 Reserved4 : 32;
1735 } Bits;
1739 UINT32 Uint32;
1743 UINT64 Uint64;
1745
1765#define MSR_IA32_DEBUGCTL 0x000001D9
1766
1770typedef union {
1774 struct {
1780 UINT32 LBR : 1;
1786 UINT32 BTF : 1;
1787 UINT32 Reserved1 : 4;
1792 UINT32 TR : 1;
1798 UINT32 BTS : 1;
1805 UINT32 BTINT : 1;
1810 UINT32 BTS_OFF_OS : 1;
1815 UINT32 BTS_OFF_USR : 1;
1842 UINT32 RTM_DEBUG : 1;
1843 UINT32 Reserved2 : 16;
1844 UINT32 Reserved3 : 32;
1845 } Bits;
1849 UINT32 Uint32;
1853 UINT64 Uint64;
1855
1875#define MSR_IA32_SMRR_PHYSBASE 0x000001F2
1876
1880typedef union {
1884 struct {
1888 UINT32 Type : 8;
1889 UINT32 Reserved1 : 4;
1893 UINT32 PhysBase : 20;
1894 UINT32 Reserved2 : 32;
1895 } Bits;
1899 UINT32 Uint32;
1903 UINT64 Uint64;
1905
1925#define MSR_IA32_SMRR_PHYSMASK 0x000001F3
1926
1930typedef union {
1934 struct {
1935 UINT32 Reserved1 : 11;
1939 UINT32 Valid : 1;
1943 UINT32 PhysMask : 20;
1944 UINT32 Reserved2 : 32;
1945 } Bits;
1949 UINT32 Uint32;
1953 UINT64 Uint64;
1955
1971#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
1972
1989#define MSR_IA32_CPU_DCA_CAP 0x000001F9
1990
2009#define MSR_IA32_DCA_0_CAP 0x000001FA
2010
2014typedef union {
2018 struct {
2023 UINT32 DCA_ACTIVE : 1;
2027 UINT32 TRANSACTION : 2;
2031 UINT32 DCA_TYPE : 4;
2035 UINT32 DCA_QUEUE_SIZE : 4;
2036 UINT32 Reserved1 : 2;
2041 UINT32 DCA_DELAY : 4;
2042 UINT32 Reserved2 : 7;
2046 UINT32 SW_BLOCK : 1;
2047 UINT32 Reserved3 : 1;
2051 UINT32 HW_BLOCK : 1;
2052 UINT32 Reserved4 : 5;
2053 UINT32 Reserved5 : 32;
2054 } Bits;
2058 UINT32 Uint32;
2062 UINT64 Uint64;
2064
2094#define MSR_IA32_MTRR_PHYSBASE0 0x00000200
2095#define MSR_IA32_MTRR_PHYSBASE1 0x00000202
2096#define MSR_IA32_MTRR_PHYSBASE2 0x00000204
2097#define MSR_IA32_MTRR_PHYSBASE3 0x00000206
2098#define MSR_IA32_MTRR_PHYSBASE4 0x00000208
2099#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
2100#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
2101#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
2102#define MSR_IA32_MTRR_PHYSBASE8 0x00000210
2103#define MSR_IA32_MTRR_PHYSBASE9 0x00000212
2105
2106#define MSR_IA32_MTRR_CACHE_UNCACHEABLE 0
2107#define MSR_IA32_MTRR_CACHE_WRITE_COMBINING 1
2108#define MSR_IA32_MTRR_CACHE_WRITE_THROUGH 4
2109#define MSR_IA32_MTRR_CACHE_WRITE_PROTECTED 5
2110#define MSR_IA32_MTRR_CACHE_WRITE_BACK 6
2111#define MSR_IA32_MTRR_CACHE_INVALID_TYPE 7
2112
2117typedef union {
2121 struct {
2125 UINT32 Type : 8;
2126 UINT32 Reserved1 : 4;
2130 UINT32 PhysBase : 20;
2139 UINT32 PhysBaseHi : 32;
2140 } Bits;
2144 UINT64 Uint64;
2146
2176#define MSR_IA32_MTRR_PHYSMASK0 0x00000201
2177#define MSR_IA32_MTRR_PHYSMASK1 0x00000203
2178#define MSR_IA32_MTRR_PHYSMASK2 0x00000205
2179#define MSR_IA32_MTRR_PHYSMASK3 0x00000207
2180#define MSR_IA32_MTRR_PHYSMASK4 0x00000209
2181#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
2182#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
2183#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
2184#define MSR_IA32_MTRR_PHYSMASK8 0x00000211
2185#define MSR_IA32_MTRR_PHYSMASK9 0x00000213
2187
2192typedef union {
2196 struct {
2197 UINT32 Reserved1 : 11;
2201 UINT32 V : 1;
2205 UINT32 PhysMask : 20;
2214 UINT32 PhysMaskHi : 32;
2215 } Bits;
2219 UINT64 Uint64;
2221
2238#define MSR_IA32_MTRR_FIX64K_00000 0x00000250
2239
2256#define MSR_IA32_MTRR_FIX16K_80000 0x00000258
2257
2274#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
2275
2292#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
2293
2310#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
2311
2328#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
2329
2346#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
2347
2364#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
2365
2382#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
2383
2400#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
2401
2418#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
2419
2438#define MSR_IA32_PAT 0x00000277
2439
2443typedef union {
2447 struct {
2451 UINT32 PA0 : 3;
2452 UINT32 Reserved1 : 5;
2456 UINT32 PA1 : 3;
2457 UINT32 Reserved2 : 5;
2461 UINT32 PA2 : 3;
2462 UINT32 Reserved3 : 5;
2466 UINT32 PA3 : 3;
2467 UINT32 Reserved4 : 5;
2471 UINT32 PA4 : 3;
2472 UINT32 Reserved5 : 5;
2476 UINT32 PA5 : 3;
2477 UINT32 Reserved6 : 5;
2481 UINT32 PA6 : 3;
2482 UINT32 Reserved7 : 5;
2486 UINT32 PA7 : 3;
2487 UINT32 Reserved8 : 5;
2488 } Bits;
2492 UINT64 Uint64;
2494
2546#define MSR_IA32_MC0_CTL2 0x00000280
2547#define MSR_IA32_MC1_CTL2 0x00000281
2548#define MSR_IA32_MC2_CTL2 0x00000282
2549#define MSR_IA32_MC3_CTL2 0x00000283
2550#define MSR_IA32_MC4_CTL2 0x00000284
2551#define MSR_IA32_MC5_CTL2 0x00000285
2552#define MSR_IA32_MC6_CTL2 0x00000286
2553#define MSR_IA32_MC7_CTL2 0x00000287
2554#define MSR_IA32_MC8_CTL2 0x00000288
2555#define MSR_IA32_MC9_CTL2 0x00000289
2556#define MSR_IA32_MC10_CTL2 0x0000028A
2557#define MSR_IA32_MC11_CTL2 0x0000028B
2558#define MSR_IA32_MC12_CTL2 0x0000028C
2559#define MSR_IA32_MC13_CTL2 0x0000028D
2560#define MSR_IA32_MC14_CTL2 0x0000028E
2561#define MSR_IA32_MC15_CTL2 0x0000028F
2562#define MSR_IA32_MC16_CTL2 0x00000290
2563#define MSR_IA32_MC17_CTL2 0x00000291
2564#define MSR_IA32_MC18_CTL2 0x00000292
2565#define MSR_IA32_MC19_CTL2 0x00000293
2566#define MSR_IA32_MC20_CTL2 0x00000294
2567#define MSR_IA32_MC21_CTL2 0x00000295
2568#define MSR_IA32_MC22_CTL2 0x00000296
2569#define MSR_IA32_MC23_CTL2 0x00000297
2570#define MSR_IA32_MC24_CTL2 0x00000298
2571#define MSR_IA32_MC25_CTL2 0x00000299
2572#define MSR_IA32_MC26_CTL2 0x0000029A
2573#define MSR_IA32_MC27_CTL2 0x0000029B
2574#define MSR_IA32_MC28_CTL2 0x0000029C
2575#define MSR_IA32_MC29_CTL2 0x0000029D
2576#define MSR_IA32_MC30_CTL2 0x0000029E
2577#define MSR_IA32_MC31_CTL2 0x0000029F
2579
2584typedef union {
2588 struct {
2593 UINT32 Reserved1 : 15;
2597 UINT32 CMCI_EN : 1;
2598 UINT32 Reserved2 : 1;
2599 UINT32 Reserved3 : 32;
2600 } Bits;
2604 UINT32 Uint32;
2608 UINT64 Uint64;
2610
2629#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
2630
2634typedef union {
2638 struct {
2642 UINT32 Type : 3;
2643 UINT32 Reserved1 : 7;
2647 UINT32 FE : 1;
2651 UINT32 E : 1;
2652 UINT32 Reserved2 : 20;
2653 UINT32 Reserved3 : 32;
2654 } Bits;
2658 UINT32 Uint32;
2662 UINT64 Uint64;
2664
2682#define MSR_IA32_FIXED_CTR0 0x00000309
2683
2701#define MSR_IA32_FIXED_CTR1 0x0000030A
2702
2720#define MSR_IA32_FIXED_CTR2 0x0000030B
2721
2740#define MSR_IA32_PERF_CAPABILITIES 0x00000345
2741
2745typedef union {
2749 struct {
2753 UINT32 LBR_FMT : 6;
2757 UINT32 PEBS_TRAP : 1;
2761 UINT32 PEBS_ARCH_REG : 1;
2765 UINT32 PEBS_REC_FMT : 4;
2769 UINT32 SMM_FREEZE : 1;
2773 UINT32 FW_WRITE : 1;
2774 UINT32 Reserved1 : 18;
2775 UINT32 Reserved2 : 32;
2776 } Bits;
2780 UINT32 Uint32;
2784 UINT64 Uint64;
2786
2808#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
2809
2813typedef union {
2817 struct {
2821 UINT32 EN0_OS : 1;
2825 UINT32 EN0_Usr : 1;
2833 UINT32 AnyThread0 : 1;
2837 UINT32 EN0_PMI : 1;
2841 UINT32 EN1_OS : 1;
2845 UINT32 EN1_Usr : 1;
2853 UINT32 AnyThread1 : 1;
2857 UINT32 EN1_PMI : 1;
2861 UINT32 EN2_OS : 1;
2865 UINT32 EN2_Usr : 1;
2873 UINT32 AnyThread2 : 1;
2877 UINT32 EN2_PMI : 1;
2878 UINT32 Reserved1 : 20;
2879 UINT32 Reserved2 : 32;
2880 } Bits;
2884 UINT32 Uint32;
2888 UINT64 Uint64;
2890
2908#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
2909
2913typedef union {
2917 struct {
2922 UINT32 Ovf_PMC0 : 1;
2927 UINT32 Ovf_PMC1 : 1;
2932 UINT32 Ovf_PMC2 : 1;
2937 UINT32 Ovf_PMC3 : 1;
2938 UINT32 Reserved1 : 28;
2943 UINT32 Ovf_FixedCtr0 : 1;
2948 UINT32 Ovf_FixedCtr1 : 1;
2953 UINT32 Ovf_FixedCtr2 : 1;
2954 UINT32 Reserved2 : 20;
2960 UINT32 Trace_ToPA_PMI : 1;
2961 UINT32 Reserved3 : 2;
2967 UINT32 LBR_Frz : 1;
2973 UINT32 CTR_Frz : 1;
2979 UINT32 ASCI : 1;
2984 UINT32 Ovf_Uncore : 1;
2989 UINT32 OvfBuf : 1;
2994 UINT32 CondChgd : 1;
2995 } Bits;
2999 UINT64 Uint64;
3001
3023#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
3024
3028typedef union {
3032 struct {
3038 UINT32 EN_PMCn : 32;
3044 UINT32 EN_FIXED_CTRn : 32;
3045 } Bits;
3049 UINT64 Uint64;
3051
3071#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
3072
3076typedef union {
3080 struct {
3086 UINT32 Ovf_PMCn : 32;
3093 UINT32 Ovf_FIXED_CTRn : 23;
3098 UINT32 Trace_ToPA_PMI : 1;
3099 UINT32 Reserved2 : 5;
3104 UINT32 Ovf_Uncore : 1;
3108 UINT32 OvfBuf : 1;
3112 UINT32 CondChgd : 1;
3113 } Bits;
3117 UINT64 Uint64;
3119
3139#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
3140
3144typedef union {
3148 struct {
3154 UINT32 Ovf_PMCn : 32;
3161 UINT32 Ovf_FIXED_CTRn : 23;
3166 UINT32 Trace_ToPA_PMI : 1;
3167 UINT32 Reserved2 : 2;
3171 UINT32 LBR_Frz : 1;
3175 UINT32 CTR_Frz : 1;
3179 UINT32 ASCI : 1;
3184 UINT32 Ovf_Uncore : 1;
3188 UINT32 OvfBuf : 1;
3192 UINT32 CondChgd : 1;
3193 } Bits;
3197 UINT64 Uint64;
3199
3219#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
3220
3224typedef union {
3228 struct {
3234 UINT32 Ovf_PMCn : 32;
3241 UINT32 Ovf_FIXED_CTRn : 23;
3245 UINT32 Trace_ToPA_PMI : 1;
3246 UINT32 Reserved2 : 2;
3250 UINT32 LBR_Frz : 1;
3254 UINT32 CTR_Frz : 1;
3258 UINT32 ASCI : 1;
3262 UINT32 Ovf_Uncore : 1;
3266 UINT32 OvfBuf : 1;
3267 UINT32 Reserved3 : 1;
3268 } Bits;
3272 UINT64 Uint64;
3274
3293#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
3294
3298typedef union {
3302 struct {
3308 UINT32 IA32_PERFEVTSELn : 32;
3315 UINT32 IA32_FIXED_CTRn : 31;
3319 UINT32 PMI : 1;
3320 } Bits;
3324 UINT64 Uint64;
3326
3345#define MSR_IA32_PEBS_ENABLE 0x000003F1
3346
3350typedef union {
3354 struct {
3359 UINT32 Enable : 1;
3363 UINT32 Reserved1 : 3;
3364 UINT32 Reserved2 : 28;
3368 UINT32 Reserved3 : 4;
3369 UINT32 Reserved4 : 28;
3370 } Bits;
3374 UINT64 Uint64;
3376
3422#define MSR_IA32_MC0_CTL 0x00000400
3423#define MSR_IA32_MC1_CTL 0x00000404
3424#define MSR_IA32_MC2_CTL 0x00000408
3425#define MSR_IA32_MC3_CTL 0x0000040C
3426#define MSR_IA32_MC4_CTL 0x00000410
3427#define MSR_IA32_MC5_CTL 0x00000414
3428#define MSR_IA32_MC6_CTL 0x00000418
3429#define MSR_IA32_MC7_CTL 0x0000041C
3430#define MSR_IA32_MC8_CTL 0x00000420
3431#define MSR_IA32_MC9_CTL 0x00000424
3432#define MSR_IA32_MC10_CTL 0x00000428
3433#define MSR_IA32_MC11_CTL 0x0000042C
3434#define MSR_IA32_MC12_CTL 0x00000430
3435#define MSR_IA32_MC13_CTL 0x00000434
3436#define MSR_IA32_MC14_CTL 0x00000438
3437#define MSR_IA32_MC15_CTL 0x0000043C
3438#define MSR_IA32_MC16_CTL 0x00000440
3439#define MSR_IA32_MC17_CTL 0x00000444
3440#define MSR_IA32_MC18_CTL 0x00000448
3441#define MSR_IA32_MC19_CTL 0x0000044C
3442#define MSR_IA32_MC20_CTL 0x00000450
3443#define MSR_IA32_MC21_CTL 0x00000454
3444#define MSR_IA32_MC22_CTL 0x00000458
3445#define MSR_IA32_MC23_CTL 0x0000045C
3446#define MSR_IA32_MC24_CTL 0x00000460
3447#define MSR_IA32_MC25_CTL 0x00000464
3448#define MSR_IA32_MC26_CTL 0x00000468
3449#define MSR_IA32_MC27_CTL 0x0000046C
3450#define MSR_IA32_MC28_CTL 0x00000470
3452
3498#define MSR_IA32_MC0_STATUS 0x00000401
3499#define MSR_IA32_MC1_STATUS 0x00000405
3500#define MSR_IA32_MC2_STATUS 0x00000409
3501#define MSR_IA32_MC3_STATUS 0x0000040D
3502#define MSR_IA32_MC4_STATUS 0x00000411
3503#define MSR_IA32_MC5_STATUS 0x00000415
3504#define MSR_IA32_MC6_STATUS 0x00000419
3505#define MSR_IA32_MC7_STATUS 0x0000041D
3506#define MSR_IA32_MC8_STATUS 0x00000421
3507#define MSR_IA32_MC9_STATUS 0x00000425
3508#define MSR_IA32_MC10_STATUS 0x00000429
3509#define MSR_IA32_MC11_STATUS 0x0000042D
3510#define MSR_IA32_MC12_STATUS 0x00000431
3511#define MSR_IA32_MC13_STATUS 0x00000435
3512#define MSR_IA32_MC14_STATUS 0x00000439
3513#define MSR_IA32_MC15_STATUS 0x0000043D
3514#define MSR_IA32_MC16_STATUS 0x00000441
3515#define MSR_IA32_MC17_STATUS 0x00000445
3516#define MSR_IA32_MC18_STATUS 0x00000449
3517#define MSR_IA32_MC19_STATUS 0x0000044D
3518#define MSR_IA32_MC20_STATUS 0x00000451
3519#define MSR_IA32_MC21_STATUS 0x00000455
3520#define MSR_IA32_MC22_STATUS 0x00000459
3521#define MSR_IA32_MC23_STATUS 0x0000045D
3522#define MSR_IA32_MC24_STATUS 0x00000461
3523#define MSR_IA32_MC25_STATUS 0x00000465
3524#define MSR_IA32_MC26_STATUS 0x00000469
3525#define MSR_IA32_MC27_STATUS 0x0000046D
3526#define MSR_IA32_MC28_STATUS 0x00000471
3528
3574#define MSR_IA32_MC0_ADDR 0x00000402
3575#define MSR_IA32_MC1_ADDR 0x00000406
3576#define MSR_IA32_MC2_ADDR 0x0000040A
3577#define MSR_IA32_MC3_ADDR 0x0000040E
3578#define MSR_IA32_MC4_ADDR 0x00000412
3579#define MSR_IA32_MC5_ADDR 0x00000416
3580#define MSR_IA32_MC6_ADDR 0x0000041A
3581#define MSR_IA32_MC7_ADDR 0x0000041E
3582#define MSR_IA32_MC8_ADDR 0x00000422
3583#define MSR_IA32_MC9_ADDR 0x00000426
3584#define MSR_IA32_MC10_ADDR 0x0000042A
3585#define MSR_IA32_MC11_ADDR 0x0000042E
3586#define MSR_IA32_MC12_ADDR 0x00000432
3587#define MSR_IA32_MC13_ADDR 0x00000436
3588#define MSR_IA32_MC14_ADDR 0x0000043A
3589#define MSR_IA32_MC15_ADDR 0x0000043E
3590#define MSR_IA32_MC16_ADDR 0x00000442
3591#define MSR_IA32_MC17_ADDR 0x00000446
3592#define MSR_IA32_MC18_ADDR 0x0000044A
3593#define MSR_IA32_MC19_ADDR 0x0000044E
3594#define MSR_IA32_MC20_ADDR 0x00000452
3595#define MSR_IA32_MC21_ADDR 0x00000456
3596#define MSR_IA32_MC22_ADDR 0x0000045A
3597#define MSR_IA32_MC23_ADDR 0x0000045E
3598#define MSR_IA32_MC24_ADDR 0x00000462
3599#define MSR_IA32_MC25_ADDR 0x00000466
3600#define MSR_IA32_MC26_ADDR 0x0000046A
3601#define MSR_IA32_MC27_ADDR 0x0000046E
3602#define MSR_IA32_MC28_ADDR 0x00000472
3604
3650#define MSR_IA32_MC0_MISC 0x00000403
3651#define MSR_IA32_MC1_MISC 0x00000407
3652#define MSR_IA32_MC2_MISC 0x0000040B
3653#define MSR_IA32_MC3_MISC 0x0000040F
3654#define MSR_IA32_MC4_MISC 0x00000413
3655#define MSR_IA32_MC5_MISC 0x00000417
3656#define MSR_IA32_MC6_MISC 0x0000041B
3657#define MSR_IA32_MC7_MISC 0x0000041F
3658#define MSR_IA32_MC8_MISC 0x00000423
3659#define MSR_IA32_MC9_MISC 0x00000427
3660#define MSR_IA32_MC10_MISC 0x0000042B
3661#define MSR_IA32_MC11_MISC 0x0000042F
3662#define MSR_IA32_MC12_MISC 0x00000433
3663#define MSR_IA32_MC13_MISC 0x00000437
3664#define MSR_IA32_MC14_MISC 0x0000043B
3665#define MSR_IA32_MC15_MISC 0x0000043F
3666#define MSR_IA32_MC16_MISC 0x00000443
3667#define MSR_IA32_MC17_MISC 0x00000447
3668#define MSR_IA32_MC18_MISC 0x0000044B
3669#define MSR_IA32_MC19_MISC 0x0000044F
3670#define MSR_IA32_MC20_MISC 0x00000453
3671#define MSR_IA32_MC21_MISC 0x00000457
3672#define MSR_IA32_MC22_MISC 0x0000045B
3673#define MSR_IA32_MC23_MISC 0x0000045F
3674#define MSR_IA32_MC24_MISC 0x00000463
3675#define MSR_IA32_MC25_MISC 0x00000467
3676#define MSR_IA32_MC26_MISC 0x0000046B
3677#define MSR_IA32_MC27_MISC 0x0000046F
3678#define MSR_IA32_MC28_MISC 0x00000473
3680
3697#define MSR_IA32_VMX_BASIC 0x00000480
3698
3702typedef union {
3706 struct {
3717 UINT32 VmcsRevisonId : 31;
3718 UINT32 MustBeZero : 1;
3724 UINT32 VmcsSize : 13;
3725 UINT32 Reserved1 : 3;
3744 UINT32 DualMonitor : 1;
3770 UINT32 MemoryType : 4;
3786 UINT32 VmxControls : 1;
3787 UINT32 Reserved2 : 8;
3788 } Bits;
3792 UINT64 Uint64;
3794
3798#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00
3799#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06
3803
3820#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
3821
3839#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
3840
3857#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
3858
3875#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
3876
3893#define MSR_IA32_VMX_MISC 0x00000485
3894
3898typedef union {
3902 struct {
3909 UINT32 VmxTimerRatio : 5;
3916 UINT32 VmExitEferLma : 1;
3929 UINT32 Reserved1 : 5;
3980 UINT32 Reserved2 : 1;
3986 } Bits;
3990 UINT64 Uint64;
3992
4009#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
4010
4027#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
4028
4045#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
4046
4063#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
4064
4081#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
4082
4100#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
4101
4119#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
4120
4138#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
4139
4157#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
4158
4175#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
4176
4193#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
4194
4211#define MSR_IA32_VMX_VMFUNC 0x00000491
4212
4238#define MSR_IA32_A_PMC0 0x000004C1
4239#define MSR_IA32_A_PMC1 0x000004C2
4240#define MSR_IA32_A_PMC2 0x000004C3
4241#define MSR_IA32_A_PMC3 0x000004C4
4242#define MSR_IA32_A_PMC4 0x000004C5
4243#define MSR_IA32_A_PMC5 0x000004C6
4244#define MSR_IA32_A_PMC6 0x000004C7
4245#define MSR_IA32_A_PMC7 0x000004C8
4247
4266#define MSR_IA32_MCG_EXT_CTL 0x000004D0
4267
4271typedef union {
4275 struct {
4279 UINT32 LMCE_EN : 1;
4280 UINT32 Reserved1 : 31;
4281 UINT32 Reserved2 : 32;
4282 } Bits;
4286 UINT32 Uint32;
4290 UINT64 Uint64;
4292
4311#define MSR_IA32_SGX_SVN_STATUS 0x00000500
4312
4316typedef union {
4320 struct {
4325 UINT32 Lock : 1;
4326 UINT32 Reserved1 : 15;
4331 UINT32 SGX_SVN_SINIT : 8;
4332 UINT32 Reserved2 : 8;
4333 UINT32 Reserved3 : 32;
4334 } Bits;
4338 UINT32 Uint32;
4342 UINT64 Uint64;
4344
4365#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
4366
4370typedef union {
4374 struct {
4375 UINT32 Reserved : 7;
4379 UINT32 Base : 25;
4383 UINT32 BaseHi : 32;
4384 } Bits;
4388 UINT64 Uint64;
4390
4411#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
4412
4416typedef union {
4420 struct {
4421 UINT32 Reserved : 7;
4429 UINT32 OutputOffset : 32;
4430 } Bits;
4434 UINT64 Uint64;
4436
4440typedef union {
4444 struct {
4448 UINT32 END : 1;
4449 UINT32 Reserved1 : 1;
4453 UINT32 INT : 1;
4454 UINT32 Reserved2 : 1;
4458 UINT32 STOP : 1;
4459 UINT32 Reserved3 : 1;
4464 UINT32 Size : 4;
4465 UINT32 Reserved4 : 2;
4475 UINT32 Base : 20;
4485 UINT32 BaseHi : 32;
4486 } Bits;
4490 UINT64 Uint64;
4492
4496typedef enum {
4497 RtitTopaMemorySize4K = 0,
4498 RtitTopaMemorySize8K,
4499 RtitTopaMemorySize16K,
4500 RtitTopaMemorySize32K,
4501 RtitTopaMemorySize64K,
4502 RtitTopaMemorySize128K,
4503 RtitTopaMemorySize256K,
4504 RtitTopaMemorySize512K,
4505 RtitTopaMemorySize1M,
4506 RtitTopaMemorySize2M,
4507 RtitTopaMemorySize4M,
4508 RtitTopaMemorySize8M,
4509 RtitTopaMemorySize16M,
4510 RtitTopaMemorySize32M,
4511 RtitTopaMemorySize64M,
4512 RtitTopaMemorySize128M
4514
4533#define MSR_IA32_RTIT_CTL 0x00000570
4534
4538typedef union {
4542 struct {
4546 UINT32 TraceEn : 1;
4550 UINT32 CYCEn : 1;
4554 UINT32 OS : 1;
4558 UINT32 User : 1;
4562 UINT32 PwrEvtEn : 1;
4566 UINT32 FUPonPTW : 1;
4570 UINT32 FabricEn : 1;
4574 UINT32 CR3 : 1;
4578 UINT32 ToPA : 1;
4582 UINT32 MTCEn : 1;
4586 UINT32 TSCEn : 1;
4590 UINT32 DisRETC : 1;
4594 UINT32 PTWEn : 1;
4598 UINT32 BranchEn : 1;
4602 UINT32 MTCFreq : 4;
4603 UINT32 Reserved3 : 1;
4607 UINT32 CYCThresh : 4;
4608 UINT32 Reserved4 : 1;
4612 UINT32 PSBFreq : 4;
4613 UINT32 Reserved5 : 4;
4617 UINT32 ADDR0_CFG : 4;
4621 UINT32 ADDR1_CFG : 4;
4625 UINT32 ADDR2_CFG : 4;
4629 UINT32 ADDR3_CFG : 4;
4630 UINT32 Reserved6 : 16;
4631 } Bits;
4635 UINT64 Uint64;
4637
4656#define MSR_IA32_RTIT_STATUS 0x00000571
4657
4661typedef union {
4665 struct {
4670 UINT32 FilterEn : 1;
4674 UINT32 ContexEn : 1;
4678 UINT32 TriggerEn : 1;
4679 UINT32 Reserved1 : 1;
4683 UINT32 Error : 1;
4687 UINT32 Stopped : 1;
4688 UINT32 Reserved2 : 26;
4692 UINT32 PacketByteCnt : 17;
4693 UINT32 Reserved3 : 15;
4694 } Bits;
4698 UINT64 Uint64;
4700
4720#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
4721
4725typedef union {
4729 struct {
4730 UINT32 Reserved : 5;
4734 UINT32 Cr3 : 27;
4738 UINT32 Cr3Hi : 32;
4739 } Bits;
4743 UINT64 Uint64;
4745
4768#define MSR_IA32_RTIT_ADDR0_A 0x00000580
4769#define MSR_IA32_RTIT_ADDR1_A 0x00000582
4770#define MSR_IA32_RTIT_ADDR2_A 0x00000584
4771#define MSR_IA32_RTIT_ADDR3_A 0x00000586
4773
4796#define MSR_IA32_RTIT_ADDR0_B 0x00000581
4797#define MSR_IA32_RTIT_ADDR1_B 0x00000583
4798#define MSR_IA32_RTIT_ADDR2_B 0x00000585
4799#define MSR_IA32_RTIT_ADDR3_B 0x00000587
4801
4807typedef union {
4811 struct {
4815 UINT32 VirtualAddress : 32;
4819 UINT32 VirtualAddressHi : 16;
4823 UINT32 SignExt_VA : 16;
4824 } Bits;
4828 UINT64 Uint64;
4830
4853#define MSR_IA32_DS_AREA 0x00000600
4854
4872#define MSR_IA32_TSC_DEADLINE 0x000006E0
4873
4892#define MSR_IA32_PM_ENABLE 0x00000770
4893
4897typedef union {
4901 struct {
4906 UINT32 HWP_ENABLE : 1;
4907 UINT32 Reserved1 : 31;
4908 UINT32 Reserved2 : 32;
4909 } Bits;
4913 UINT32 Uint32;
4917 UINT64 Uint64;
4919
4937#define MSR_IA32_HWP_CAPABILITIES 0x00000771
4938
4942typedef union {
4946 struct {
4967 UINT32 Reserved : 32;
4968 } Bits;
4972 UINT32 Uint32;
4976 UINT64 Uint64;
4978
4998#define MSR_IA32_HWP_REQUEST_PKG 0x00000772
4999
5003typedef union {
5007 struct {
5032 UINT32 Activity_Window : 10;
5033 UINT32 Reserved : 22;
5034 } Bits;
5038 UINT64 Uint64;
5040
5059#define MSR_IA32_HWP_INTERRUPT 0x00000773
5060
5064typedef union {
5068 struct {
5079 UINT32 Reserved1 : 30;
5080 UINT32 Reserved2 : 32;
5081 } Bits;
5085 UINT32 Uint32;
5089 UINT64 Uint64;
5091
5111#define MSR_IA32_HWP_REQUEST 0x00000774
5112
5116typedef union {
5120 struct {
5145 UINT32 Activity_Window : 10;
5151 UINT32 Reserved : 21;
5152 } Bits;
5156 UINT64 Uint64;
5158
5178#define MSR_IA32_HWP_STATUS 0x00000777
5179
5183typedef union {
5187 struct {
5193 UINT32 Reserved1 : 1;
5199 UINT32 Reserved2 : 29;
5200 UINT32 Reserved3 : 32;
5201 } Bits;
5205 UINT32 Uint32;
5209 UINT64 Uint64;
5211
5228#define MSR_IA32_X2APIC_APICID 0x00000802
5229
5246#define MSR_IA32_X2APIC_VERSION 0x00000803
5247
5265#define MSR_IA32_X2APIC_TPR 0x00000808
5266
5283#define MSR_IA32_X2APIC_PPR 0x0000080A
5284
5302#define MSR_IA32_X2APIC_EOI 0x0000080B
5303
5320#define MSR_IA32_X2APIC_LDR 0x0000080D
5321
5339#define MSR_IA32_X2APIC_SIVR 0x0000080F
5340
5365#define MSR_IA32_X2APIC_ISR0 0x00000810
5366#define MSR_IA32_X2APIC_ISR1 0x00000811
5367#define MSR_IA32_X2APIC_ISR2 0x00000812
5368#define MSR_IA32_X2APIC_ISR3 0x00000813
5369#define MSR_IA32_X2APIC_ISR4 0x00000814
5370#define MSR_IA32_X2APIC_ISR5 0x00000815
5371#define MSR_IA32_X2APIC_ISR6 0x00000816
5372#define MSR_IA32_X2APIC_ISR7 0x00000817
5374
5399#define MSR_IA32_X2APIC_TMR0 0x00000818
5400#define MSR_IA32_X2APIC_TMR1 0x00000819
5401#define MSR_IA32_X2APIC_TMR2 0x0000081A
5402#define MSR_IA32_X2APIC_TMR3 0x0000081B
5403#define MSR_IA32_X2APIC_TMR4 0x0000081C
5404#define MSR_IA32_X2APIC_TMR5 0x0000081D
5405#define MSR_IA32_X2APIC_TMR6 0x0000081E
5406#define MSR_IA32_X2APIC_TMR7 0x0000081F
5408
5433#define MSR_IA32_X2APIC_IRR0 0x00000820
5434#define MSR_IA32_X2APIC_IRR1 0x00000821
5435#define MSR_IA32_X2APIC_IRR2 0x00000822
5436#define MSR_IA32_X2APIC_IRR3 0x00000823
5437#define MSR_IA32_X2APIC_IRR4 0x00000824
5438#define MSR_IA32_X2APIC_IRR5 0x00000825
5439#define MSR_IA32_X2APIC_IRR6 0x00000826
5440#define MSR_IA32_X2APIC_IRR7 0x00000827
5442
5460#define MSR_IA32_X2APIC_ESR 0x00000828
5461
5479#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
5480
5498#define MSR_IA32_X2APIC_ICR 0x00000830
5499
5517#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
5518
5536#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
5537
5555#define MSR_IA32_X2APIC_LVT_PMI 0x00000834
5556
5574#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
5575
5593#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
5594
5612#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
5613
5631#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
5632
5649#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
5650
5668#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
5669
5687#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
5688
5707#define MSR_IA32_TME_ACTIVATE 0x00000982
5708
5712typedef union {
5716 struct {
5721 UINT32 Lock : 1;
5726 UINT32 TmeEnable : 1;
5732 UINT32 KeySelect : 1;
5748 UINT32 TmePolicy : 4;
5749 UINT32 Reserved : 23;
5759 UINT32 TmeBypassMode : 1;
5770 UINT32 MkTmeKeyidBits : 4;
5771 UINT32 Reserved2 : 12;
5781 UINT32 MkTmeCryptoAlgs : 16;
5782 } Bits;
5786 UINT32 Uint32[2];
5790 UINT64 Uint64;
5792
5811#define MSR_IA32_DEBUG_INTERFACE 0x00000C80
5812
5816typedef union {
5820 struct {
5825 UINT32 Enable : 1;
5826 UINT32 Reserved1 : 29;
5832 UINT32 Lock : 1;
5837 UINT32 DebugOccurred : 1;
5838 UINT32 Reserved2 : 32;
5839 } Bits;
5843 UINT32 Uint32;
5847 UINT64 Uint64;
5849
5868#define MSR_IA32_L3_QOS_CFG 0x00000C81
5869
5873typedef union {
5877 struct {
5882 UINT32 Enable : 1;
5883 UINT32 Reserved1 : 31;
5884 UINT32 Reserved2 : 32;
5885 } Bits;
5889 UINT32 Uint32;
5893 UINT64 Uint64;
5895
5914#define MSR_IA32_L2_QOS_CFG 0x00000C82
5915
5919typedef union {
5923 struct {
5928 UINT32 Enable : 1;
5929 UINT32 Reserved1 : 31;
5930 UINT32 Reserved2 : 32;
5931 } Bits;
5935 UINT32 Uint32;
5939 UINT64 Uint64;
5941
5961#define MSR_IA32_QM_EVTSEL 0x00000C8D
5962
5966typedef union {
5970 struct {
5975 UINT32 EventID : 8;
5976 UINT32 Reserved : 24;
5983 } Bits;
5987 UINT64 Uint64;
5989
6008#define MSR_IA32_QM_CTR 0x00000C8E
6009
6013typedef union {
6017 struct {
6030 UINT32 Unavailable : 1;
6035 UINT32 Error : 1;
6036 } Bits;
6040 UINT64 Uint64;
6042
6062#define MSR_IA32_PQR_ASSOC 0x00000C8F
6063
6067typedef union {
6071 struct {
6083 UINT32 COS : 32;
6084 } Bits;
6088 UINT64 Uint64;
6090
6110#define MSR_IA32_BNDCFGS 0x00000D90
6111
6115typedef union {
6119 struct {
6123 UINT32 EN : 1;
6128 UINT32 BNDPRESERVE : 1;
6129 UINT32 Reserved : 10;
6133 UINT32 Base : 20;
6137 UINT32 BaseHi : 32;
6138 } Bits;
6142 UINT64 Uint64;
6144
6163#define MSR_IA32_XSS 0x00000DA0
6164
6168typedef union {
6172 struct {
6173 UINT32 Reserved1 : 8;
6178 UINT32 Reserved2 : 23;
6179 UINT32 Reserved3 : 32;
6180 } Bits;
6184 UINT32 Uint32;
6188 UINT64 Uint64;
6190
6209#define MSR_IA32_PKG_HDC_CTL 0x00000DB0
6210
6214typedef union {
6218 struct {
6224 UINT32 HDC_Pkg_Enable : 1;
6225 UINT32 Reserved1 : 31;
6226 UINT32 Reserved2 : 32;
6227 } Bits;
6231 UINT32 Uint32;
6235 UINT64 Uint64;
6237
6256#define MSR_IA32_PM_CTL1 0x00000DB1
6257
6261typedef union {
6265 struct {
6272 UINT32 Reserved1 : 31;
6273 UINT32 Reserved2 : 32;
6274 } Bits;
6278 UINT32 Uint32;
6282 UINT64 Uint64;
6284
6302#define MSR_IA32_THREAD_STALL 0x00000DB2
6303
6323#define MSR_IA32_EFER 0xC0000080
6324
6328typedef union {
6332 struct {
6337 UINT32 SCE : 1;
6338 UINT32 Reserved1 : 7;
6343 UINT32 LME : 1;
6344 UINT32 Reserved2 : 1;
6349 UINT32 LMA : 1;
6353 UINT32 NXE : 1;
6354 UINT32 Reserved3 : 20;
6355 UINT32 Reserved4 : 32;
6356 } Bits;
6360 UINT32 Uint32;
6364 UINT64 Uint64;
6366
6383#define MSR_IA32_STAR 0xC0000081
6384
6401#define MSR_IA32_LSTAR 0xC0000082
6402
6421#define MSR_IA32_CSTAR 0xC0000083
6422
6439#define MSR_IA32_FMASK 0xC0000084
6440
6457#define MSR_IA32_FS_BASE 0xC0000100
6458
6475#define MSR_IA32_GS_BASE 0xC0000101
6476
6493#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
6494
6513#define MSR_IA32_TSC_AUX 0xC0000103
6514
6518typedef union {
6522 struct {
6526 UINT32 AUX : 32;
6527 UINT32 Reserved : 32;
6528 } Bits;
6532 UINT32 Uint32;
6536 UINT64 Uint64;
6538
6539#endif
RTIT_TOPA_MEMORY_SIZE
UINT32 MsegHeaderRevision
UINT32 MonitorFeatures