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ArchitecturalMsr.h
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1
18#ifndef __INTEL_ARCHITECTURAL_MSR_H__
19#define __INTEL_ARCHITECTURAL_MSR_H__
20
37#define MSR_IA32_P5_MC_ADDR 0x00000000
38
55#define MSR_IA32_P5_MC_TYPE 0x00000001
56
74#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
75
93#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
94
114#define MSR_IA32_PLATFORM_ID 0x00000017
115
119typedef union {
123 struct {
124 UINT32 Reserved1 : 32;
125 UINT32 Reserved2 : 18;
140 UINT32 PlatformId : 3;
141 UINT32 Reserved3 : 11;
142 } Bits;
146 UINT64 Uint64;
148
167#define MSR_IA32_APIC_BASE 0x0000001B
168
172typedef union {
176 struct {
177 UINT32 Reserved1 : 8;
181 UINT32 BSP : 1;
182 UINT32 Reserved2 : 1;
187 UINT32 EXTD : 1;
191 UINT32 EN : 1;
195 UINT32 ApicBase : 20;
199 UINT32 ApicBaseHi : 32;
200 } Bits;
204 UINT64 Uint64;
206
226#define MSR_IA32_FEATURE_CONTROL 0x0000003A
227
231typedef union {
235 struct {
247 UINT32 Lock : 1;
264 UINT32 Reserved1 : 5;
278 UINT32 Reserved2 : 1;
289 UINT32 SgxEnable : 1;
290 UINT32 Reserved3 : 1;
296 UINT32 LmceOn : 1;
297 UINT32 Reserved4 : 11;
298 UINT32 Reserved5 : 32;
299 } Bits;
303 UINT32 Uint32;
307 UINT64 Uint64;
309
330#define MSR_IA32_TSC_ADJUST 0x0000003B
331
352#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
353
374#define MSR_IA32_BIOS_SIGN_ID 0x0000008B
375
379typedef union {
383 struct {
384 UINT32 Reserved : 32;
395 } Bits;
399 UINT64 Uint64;
401
426#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
427#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
428#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
429#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
431
451#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
452
456typedef union {
460 struct {
468 UINT32 Valid : 1;
469 UINT32 Reserved1 : 1;
474 UINT32 BlockSmi : 1;
475 UINT32 Reserved2 : 9;
479 UINT32 MsegBase : 20;
480 UINT32 Reserved3 : 32;
481 } Bits;
485 UINT32 Uint32;
489 UINT64 Uint64;
491
496typedef struct {
503 //
511 UINT32 GdtrLimit;
512 UINT32 GdtrBaseOffset;
513 UINT32 CsSelector;
514 UINT32 EipOffset;
515 UINT32 EspOffset;
516 UINT32 Cr3Offset;
520 UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
522
526#define STM_FEATURES_IA32E 0x1
530
547#define MSR_IA32_SMBASE 0x0000009E
548
574#define MSR_IA32_PMC0 0x000000C1
575#define MSR_IA32_PMC1 0x000000C2
576#define MSR_IA32_PMC2 0x000000C3
577#define MSR_IA32_PMC3 0x000000C4
578#define MSR_IA32_PMC4 0x000000C5
579#define MSR_IA32_PMC5 0x000000C6
580#define MSR_IA32_PMC6 0x000000C7
581#define MSR_IA32_PMC7 0x000000C8
583
603#define MSR_IA32_MPERF 0x000000E7
604
624#define MSR_IA32_APERF 0x000000E8
625
644#define MSR_IA32_MTRRCAP 0x000000FE
645
649typedef union {
653 struct {
658 UINT32 VCNT : 8;
662 UINT32 FIX : 1;
663 UINT32 Reserved1 : 1;
667 UINT32 WC : 1;
671 UINT32 SMRR : 1;
672 UINT32 Reserved2 : 20;
673 UINT32 Reserved3 : 32;
674 } Bits;
678 UINT32 Uint32;
682 UINT64 Uint64;
684
703#define MSR_IA32_SYSENTER_CS 0x00000174
704
708typedef union {
712 struct {
716 UINT32 CS : 16;
717 UINT32 Reserved1 : 16;
718 UINT32 Reserved2 : 32;
719 } Bits;
723 UINT32 Uint32;
727 UINT64 Uint64;
729
746#define MSR_IA32_SYSENTER_ESP 0x00000175
747
764#define MSR_IA32_SYSENTER_EIP 0x00000176
765
784#define MSR_IA32_MCG_CAP 0x00000179
785
789typedef union {
793 struct {
797 UINT32 Count : 8;
801 UINT32 MCG_CTL_P : 1;
806 UINT32 MCG_EXT_P : 1;
811 UINT32 MCP_CMCI_P : 1;
816 UINT32 MCG_TES_P : 1;
817 UINT32 Reserved1 : 4;
822 UINT32 MCG_EXT_CNT : 8;
827 UINT32 MCG_SER_P : 1;
828 UINT32 Reserved2 : 1;
837 UINT32 MCG_ELOG_P : 1;
844 UINT32 MCG_LMCE_P : 1;
845 UINT32 Reserved3 : 4;
846 UINT32 Reserved4 : 32;
847 } Bits;
851 UINT32 Uint32;
855 UINT64 Uint64;
857
877#define MSR_IA32_MCG_STATUS 0x0000017A
878
882typedef union {
886 struct {
891 UINT32 RIPV : 1;
896 UINT32 EIPV : 1;
901 UINT32 MCIP : 1;
905 UINT32 LMCE_S : 1;
906 UINT32 Reserved1 : 28;
907 UINT32 Reserved2 : 32;
908 } Bits;
912 UINT32 Uint32;
916 UINT64 Uint64;
918
935#define MSR_IA32_MCG_CTL 0x0000017B
936
959#define MSR_IA32_PERFEVTSEL0 0x00000186
960#define MSR_IA32_PERFEVTSEL1 0x00000187
961#define MSR_IA32_PERFEVTSEL2 0x00000188
962#define MSR_IA32_PERFEVTSEL3 0x00000189
964
969typedef union {
973 struct {
977 UINT32 EventSelect : 8;
982 UINT32 UMASK : 8;
986 UINT32 USR : 1;
990 UINT32 OS : 1;
994 UINT32 E : 1;
998 UINT32 PC : 1;
1002 UINT32 INT : 1;
1010 UINT32 ANY : 1;
1015 UINT32 EN : 1;
1019 UINT32 INV : 1;
1025 UINT32 CMASK : 8;
1026 UINT32 Reserved : 32;
1027 } Bits;
1031 UINT32 Uint32;
1035 UINT64 Uint64;
1037
1056#define MSR_IA32_PERF_STATUS 0x00000198
1057
1061typedef union {
1065 struct {
1069 UINT32 State : 16;
1070 UINT32 Reserved1 : 16;
1071 UINT32 Reserved2 : 32;
1072 } Bits;
1076 UINT32 Uint32;
1080 UINT64 Uint64;
1082
1101#define MSR_IA32_PERF_CTL 0x00000199
1102
1106typedef union {
1110 struct {
1114 UINT32 TargetState : 16;
1115 UINT32 Reserved1 : 16;
1120 UINT32 IDA : 1;
1121 UINT32 Reserved2 : 31;
1122 } Bits;
1126 UINT64 Uint64;
1128
1148#define MSR_IA32_CLOCK_MODULATION 0x0000019A
1149
1153typedef union {
1157 struct {
1173 UINT32 Reserved1 : 27;
1174 UINT32 Reserved2 : 32;
1175 } Bits;
1179 UINT32 Uint32;
1183 UINT64 Uint64;
1185
1207#define MSR_IA32_THERM_INTERRUPT 0x0000019B
1208
1212typedef union {
1216 struct {
1220 UINT32 HighTempEnable : 1;
1224 UINT32 LowTempEnable : 1;
1228 UINT32 PROCHOT_Enable : 1;
1232 UINT32 FORCEPR_Enable : 1;
1238 UINT32 Reserved1 : 3;
1242 UINT32 Threshold1 : 7;
1250 UINT32 Threshold2 : 7;
1259 UINT32 Reserved2 : 7;
1260 UINT32 Reserved3 : 32;
1261 } Bits;
1265 UINT32 Uint32;
1269 UINT64 Uint64;
1271
1291#define MSR_IA32_THERM_STATUS 0x0000019C
1292
1296typedef union {
1300 struct {
1304 UINT32 ThermalStatus : 1;
1349 UINT32 PowerLimitLog : 1;
1369 UINT32 DigitalReadout : 7;
1370 UINT32 Reserved1 : 4;
1379 UINT32 ReadingValid : 1;
1380 UINT32 Reserved2 : 32;
1381 } Bits;
1385 UINT32 Uint32;
1389 UINT64 Uint64;
1391
1411#define MSR_IA32_MISC_ENABLE 0x000001A0
1412
1416typedef union {
1420 struct {
1426 UINT32 FastStrings : 1;
1427 UINT32 Reserved1 : 2;
1440 UINT32 Reserved2 : 3;
1447 UINT32 Reserved3 : 3;
1453 UINT32 BTS : 1;
1459 UINT32 PEBS : 1;
1460 UINT32 Reserved4 : 3;
1466 UINT32 EIST : 1;
1467 UINT32 Reserved5 : 1;
1480 UINT32 MONITOR : 1;
1481 UINT32 Reserved6 : 3;
1502 UINT32 Reserved7 : 8;
1503 UINT32 Reserved8 : 2;
1514 UINT32 XD : 1;
1515 UINT32 Reserved9 : 29;
1516 } Bits;
1520 UINT64 Uint64;
1522
1541#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
1542
1546typedef union {
1550 struct {
1556 UINT32 Reserved1 : 28;
1557 UINT32 Reserved2 : 32;
1558 } Bits;
1562 UINT32 Uint32;
1566 UINT64 Uint64;
1568
1588#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
1589
1593typedef union {
1597 struct {
1601 UINT32 ThermalStatus : 1;
1609 UINT32 PROCHOT_Event : 1;
1613 UINT32 PROCHOT_Log : 1;
1645 UINT32 PowerLimitLog : 1;
1646 UINT32 Reserved1 : 4;
1650 UINT32 DigitalReadout : 7;
1651 UINT32 Reserved2 : 9;
1652 UINT32 Reserved3 : 32;
1653 } Bits;
1657 UINT32 Uint32;
1661 UINT64 Uint64;
1663
1685#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
1686
1690typedef union {
1694 struct {
1698 UINT32 HighTempEnable : 1;
1702 UINT32 LowTempEnable : 1;
1706 UINT32 PROCHOT_Enable : 1;
1707 UINT32 Reserved1 : 1;
1711 UINT32 OverheatEnable : 1;
1712 UINT32 Reserved2 : 3;
1716 UINT32 Threshold1 : 7;
1724 UINT32 Threshold2 : 7;
1733 UINT32 Reserved3 : 7;
1734 UINT32 Reserved4 : 32;
1735 } Bits;
1739 UINT32 Uint32;
1743 UINT64 Uint64;
1745
1765#define MSR_IA32_DEBUGCTL 0x000001D9
1766
1770typedef union {
1774 struct {
1780 UINT32 LBR : 1;
1786 UINT32 BTF : 1;
1787 UINT32 Reserved1 : 4;
1792 UINT32 TR : 1;
1798 UINT32 BTS : 1;
1805 UINT32 BTINT : 1;
1810 UINT32 BTS_OFF_OS : 1;
1815 UINT32 BTS_OFF_USR : 1;
1842 UINT32 RTM_DEBUG : 1;
1843 UINT32 Reserved2 : 16;
1844 UINT32 Reserved3 : 32;
1845 } Bits;
1849 UINT32 Uint32;
1853 UINT64 Uint64;
1855
1875#define MSR_IA32_SMRR_PHYSBASE 0x000001F2
1876
1880typedef union {
1884 struct {
1888 UINT32 Type : 8;
1889 UINT32 Reserved1 : 4;
1893 UINT32 PhysBase : 20;
1894 UINT32 Reserved2 : 32;
1895 } Bits;
1899 UINT32 Uint32;
1903 UINT64 Uint64;
1905
1925#define MSR_IA32_SMRR_PHYSMASK 0x000001F3
1926
1930typedef union {
1934 struct {
1935 UINT32 Reserved1 : 11;
1939 UINT32 Valid : 1;
1943 UINT32 PhysMask : 20;
1944 UINT32 Reserved2 : 32;
1945 } Bits;
1949 UINT32 Uint32;
1953 UINT64 Uint64;
1955
1971#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
1972
1989#define MSR_IA32_CPU_DCA_CAP 0x000001F9
1990
2009#define MSR_IA32_DCA_0_CAP 0x000001FA
2010
2014typedef union {
2018 struct {
2023 UINT32 DCA_ACTIVE : 1;
2027 UINT32 TRANSACTION : 2;
2031 UINT32 DCA_TYPE : 4;
2035 UINT32 DCA_QUEUE_SIZE : 4;
2036 UINT32 Reserved1 : 2;
2041 UINT32 DCA_DELAY : 4;
2042 UINT32 Reserved2 : 7;
2046 UINT32 SW_BLOCK : 1;
2047 UINT32 Reserved3 : 1;
2051 UINT32 HW_BLOCK : 1;
2052 UINT32 Reserved4 : 5;
2053 UINT32 Reserved5 : 32;
2054 } Bits;
2058 UINT32 Uint32;
2062 UINT64 Uint64;
2064
2094#define MSR_IA32_MTRR_PHYSBASE0 0x00000200
2095#define MSR_IA32_MTRR_PHYSBASE1 0x00000202
2096#define MSR_IA32_MTRR_PHYSBASE2 0x00000204
2097#define MSR_IA32_MTRR_PHYSBASE3 0x00000206
2098#define MSR_IA32_MTRR_PHYSBASE4 0x00000208
2099#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
2100#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
2101#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
2102#define MSR_IA32_MTRR_PHYSBASE8 0x00000210
2103#define MSR_IA32_MTRR_PHYSBASE9 0x00000212
2105
2110typedef union {
2114 struct {
2118 UINT32 Type : 8;
2119 UINT32 Reserved1 : 4;
2123 UINT32 PhysBase : 20;
2132 UINT32 PhysBaseHi : 32;
2133 } Bits;
2137 UINT64 Uint64;
2139
2169#define MSR_IA32_MTRR_PHYSMASK0 0x00000201
2170#define MSR_IA32_MTRR_PHYSMASK1 0x00000203
2171#define MSR_IA32_MTRR_PHYSMASK2 0x00000205
2172#define MSR_IA32_MTRR_PHYSMASK3 0x00000207
2173#define MSR_IA32_MTRR_PHYSMASK4 0x00000209
2174#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
2175#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
2176#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
2177#define MSR_IA32_MTRR_PHYSMASK8 0x00000211
2178#define MSR_IA32_MTRR_PHYSMASK9 0x00000213
2180
2185typedef union {
2189 struct {
2190 UINT32 Reserved1 : 11;
2194 UINT32 V : 1;
2198 UINT32 PhysMask : 20;
2207 UINT32 PhysMaskHi : 32;
2208 } Bits;
2212 UINT64 Uint64;
2214
2231#define MSR_IA32_MTRR_FIX64K_00000 0x00000250
2232
2249#define MSR_IA32_MTRR_FIX16K_80000 0x00000258
2250
2267#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
2268
2285#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
2286
2303#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
2304
2321#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
2322
2339#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
2340
2357#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
2358
2375#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
2376
2393#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
2394
2411#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
2412
2431#define MSR_IA32_PAT 0x00000277
2432
2436typedef union {
2440 struct {
2444 UINT32 PA0 : 3;
2445 UINT32 Reserved1 : 5;
2449 UINT32 PA1 : 3;
2450 UINT32 Reserved2 : 5;
2454 UINT32 PA2 : 3;
2455 UINT32 Reserved3 : 5;
2459 UINT32 PA3 : 3;
2460 UINT32 Reserved4 : 5;
2464 UINT32 PA4 : 3;
2465 UINT32 Reserved5 : 5;
2469 UINT32 PA5 : 3;
2470 UINT32 Reserved6 : 5;
2474 UINT32 PA6 : 3;
2475 UINT32 Reserved7 : 5;
2479 UINT32 PA7 : 3;
2480 UINT32 Reserved8 : 5;
2481 } Bits;
2485 UINT64 Uint64;
2487
2539#define MSR_IA32_MC0_CTL2 0x00000280
2540#define MSR_IA32_MC1_CTL2 0x00000281
2541#define MSR_IA32_MC2_CTL2 0x00000282
2542#define MSR_IA32_MC3_CTL2 0x00000283
2543#define MSR_IA32_MC4_CTL2 0x00000284
2544#define MSR_IA32_MC5_CTL2 0x00000285
2545#define MSR_IA32_MC6_CTL2 0x00000286
2546#define MSR_IA32_MC7_CTL2 0x00000287
2547#define MSR_IA32_MC8_CTL2 0x00000288
2548#define MSR_IA32_MC9_CTL2 0x00000289
2549#define MSR_IA32_MC10_CTL2 0x0000028A
2550#define MSR_IA32_MC11_CTL2 0x0000028B
2551#define MSR_IA32_MC12_CTL2 0x0000028C
2552#define MSR_IA32_MC13_CTL2 0x0000028D
2553#define MSR_IA32_MC14_CTL2 0x0000028E
2554#define MSR_IA32_MC15_CTL2 0x0000028F
2555#define MSR_IA32_MC16_CTL2 0x00000290
2556#define MSR_IA32_MC17_CTL2 0x00000291
2557#define MSR_IA32_MC18_CTL2 0x00000292
2558#define MSR_IA32_MC19_CTL2 0x00000293
2559#define MSR_IA32_MC20_CTL2 0x00000294
2560#define MSR_IA32_MC21_CTL2 0x00000295
2561#define MSR_IA32_MC22_CTL2 0x00000296
2562#define MSR_IA32_MC23_CTL2 0x00000297
2563#define MSR_IA32_MC24_CTL2 0x00000298
2564#define MSR_IA32_MC25_CTL2 0x00000299
2565#define MSR_IA32_MC26_CTL2 0x0000029A
2566#define MSR_IA32_MC27_CTL2 0x0000029B
2567#define MSR_IA32_MC28_CTL2 0x0000029C
2568#define MSR_IA32_MC29_CTL2 0x0000029D
2569#define MSR_IA32_MC30_CTL2 0x0000029E
2570#define MSR_IA32_MC31_CTL2 0x0000029F
2572
2577typedef union {
2581 struct {
2586 UINT32 Reserved1 : 15;
2590 UINT32 CMCI_EN : 1;
2591 UINT32 Reserved2 : 1;
2592 UINT32 Reserved3 : 32;
2593 } Bits;
2597 UINT32 Uint32;
2601 UINT64 Uint64;
2603
2622#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
2623
2627typedef union {
2631 struct {
2635 UINT32 Type : 3;
2636 UINT32 Reserved1 : 7;
2640 UINT32 FE : 1;
2644 UINT32 E : 1;
2645 UINT32 Reserved2 : 20;
2646 UINT32 Reserved3 : 32;
2647 } Bits;
2651 UINT32 Uint32;
2655 UINT64 Uint64;
2657
2675#define MSR_IA32_FIXED_CTR0 0x00000309
2676
2694#define MSR_IA32_FIXED_CTR1 0x0000030A
2695
2713#define MSR_IA32_FIXED_CTR2 0x0000030B
2714
2733#define MSR_IA32_PERF_CAPABILITIES 0x00000345
2734
2738typedef union {
2742 struct {
2746 UINT32 LBR_FMT : 6;
2750 UINT32 PEBS_TRAP : 1;
2754 UINT32 PEBS_ARCH_REG : 1;
2758 UINT32 PEBS_REC_FMT : 4;
2762 UINT32 SMM_FREEZE : 1;
2766 UINT32 FW_WRITE : 1;
2767 UINT32 Reserved1 : 18;
2768 UINT32 Reserved2 : 32;
2769 } Bits;
2773 UINT32 Uint32;
2777 UINT64 Uint64;
2779
2801#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
2802
2806typedef union {
2810 struct {
2814 UINT32 EN0_OS : 1;
2818 UINT32 EN0_Usr : 1;
2826 UINT32 AnyThread0 : 1;
2830 UINT32 EN0_PMI : 1;
2834 UINT32 EN1_OS : 1;
2838 UINT32 EN1_Usr : 1;
2846 UINT32 AnyThread1 : 1;
2850 UINT32 EN1_PMI : 1;
2854 UINT32 EN2_OS : 1;
2858 UINT32 EN2_Usr : 1;
2866 UINT32 AnyThread2 : 1;
2870 UINT32 EN2_PMI : 1;
2871 UINT32 Reserved1 : 20;
2872 UINT32 Reserved2 : 32;
2873 } Bits;
2877 UINT32 Uint32;
2881 UINT64 Uint64;
2883
2901#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
2902
2906typedef union {
2910 struct {
2915 UINT32 Ovf_PMC0 : 1;
2920 UINT32 Ovf_PMC1 : 1;
2925 UINT32 Ovf_PMC2 : 1;
2930 UINT32 Ovf_PMC3 : 1;
2931 UINT32 Reserved1 : 28;
2936 UINT32 Ovf_FixedCtr0 : 1;
2941 UINT32 Ovf_FixedCtr1 : 1;
2946 UINT32 Ovf_FixedCtr2 : 1;
2947 UINT32 Reserved2 : 20;
2953 UINT32 Trace_ToPA_PMI : 1;
2954 UINT32 Reserved3 : 2;
2960 UINT32 LBR_Frz : 1;
2966 UINT32 CTR_Frz : 1;
2972 UINT32 ASCI : 1;
2977 UINT32 Ovf_Uncore : 1;
2982 UINT32 OvfBuf : 1;
2987 UINT32 CondChgd : 1;
2988 } Bits;
2992 UINT64 Uint64;
2994
3016#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
3017
3021typedef union {
3025 struct {
3031 UINT32 EN_PMCn : 32;
3037 UINT32 EN_FIXED_CTRn : 32;
3038 } Bits;
3042 UINT64 Uint64;
3044
3064#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
3065
3069typedef union {
3073 struct {
3079 UINT32 Ovf_PMCn : 32;
3086 UINT32 Ovf_FIXED_CTRn : 23;
3091 UINT32 Trace_ToPA_PMI : 1;
3092 UINT32 Reserved2 : 5;
3097 UINT32 Ovf_Uncore : 1;
3101 UINT32 OvfBuf : 1;
3105 UINT32 CondChgd : 1;
3106 } Bits;
3110 UINT64 Uint64;
3112
3132#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
3133
3137typedef union {
3141 struct {
3147 UINT32 Ovf_PMCn : 32;
3154 UINT32 Ovf_FIXED_CTRn : 23;
3159 UINT32 Trace_ToPA_PMI : 1;
3160 UINT32 Reserved2 : 2;
3164 UINT32 LBR_Frz : 1;
3168 UINT32 CTR_Frz : 1;
3172 UINT32 ASCI : 1;
3177 UINT32 Ovf_Uncore : 1;
3181 UINT32 OvfBuf : 1;
3185 UINT32 CondChgd : 1;
3186 } Bits;
3190 UINT64 Uint64;
3192
3212#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
3213
3217typedef union {
3221 struct {
3227 UINT32 Ovf_PMCn : 32;
3234 UINT32 Ovf_FIXED_CTRn : 23;
3238 UINT32 Trace_ToPA_PMI : 1;
3239 UINT32 Reserved2 : 2;
3243 UINT32 LBR_Frz : 1;
3247 UINT32 CTR_Frz : 1;
3251 UINT32 ASCI : 1;
3255 UINT32 Ovf_Uncore : 1;
3259 UINT32 OvfBuf : 1;
3260 UINT32 Reserved3 : 1;
3261 } Bits;
3265 UINT64 Uint64;
3267
3286#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
3287
3291typedef union {
3295 struct {
3301 UINT32 IA32_PERFEVTSELn : 32;
3308 UINT32 IA32_FIXED_CTRn : 31;
3312 UINT32 PMI : 1;
3313 } Bits;
3317 UINT64 Uint64;
3319
3338#define MSR_IA32_PEBS_ENABLE 0x000003F1
3339
3343typedef union {
3347 struct {
3352 UINT32 Enable : 1;
3356 UINT32 Reserved1 : 3;
3357 UINT32 Reserved2 : 28;
3361 UINT32 Reserved3 : 4;
3362 UINT32 Reserved4 : 28;
3363 } Bits;
3367 UINT64 Uint64;
3369
3415#define MSR_IA32_MC0_CTL 0x00000400
3416#define MSR_IA32_MC1_CTL 0x00000404
3417#define MSR_IA32_MC2_CTL 0x00000408
3418#define MSR_IA32_MC3_CTL 0x0000040C
3419#define MSR_IA32_MC4_CTL 0x00000410
3420#define MSR_IA32_MC5_CTL 0x00000414
3421#define MSR_IA32_MC6_CTL 0x00000418
3422#define MSR_IA32_MC7_CTL 0x0000041C
3423#define MSR_IA32_MC8_CTL 0x00000420
3424#define MSR_IA32_MC9_CTL 0x00000424
3425#define MSR_IA32_MC10_CTL 0x00000428
3426#define MSR_IA32_MC11_CTL 0x0000042C
3427#define MSR_IA32_MC12_CTL 0x00000430
3428#define MSR_IA32_MC13_CTL 0x00000434
3429#define MSR_IA32_MC14_CTL 0x00000438
3430#define MSR_IA32_MC15_CTL 0x0000043C
3431#define MSR_IA32_MC16_CTL 0x00000440
3432#define MSR_IA32_MC17_CTL 0x00000444
3433#define MSR_IA32_MC18_CTL 0x00000448
3434#define MSR_IA32_MC19_CTL 0x0000044C
3435#define MSR_IA32_MC20_CTL 0x00000450
3436#define MSR_IA32_MC21_CTL 0x00000454
3437#define MSR_IA32_MC22_CTL 0x00000458
3438#define MSR_IA32_MC23_CTL 0x0000045C
3439#define MSR_IA32_MC24_CTL 0x00000460
3440#define MSR_IA32_MC25_CTL 0x00000464
3441#define MSR_IA32_MC26_CTL 0x00000468
3442#define MSR_IA32_MC27_CTL 0x0000046C
3443#define MSR_IA32_MC28_CTL 0x00000470
3445
3491#define MSR_IA32_MC0_STATUS 0x00000401
3492#define MSR_IA32_MC1_STATUS 0x00000405
3493#define MSR_IA32_MC2_STATUS 0x00000409
3494#define MSR_IA32_MC3_STATUS 0x0000040D
3495#define MSR_IA32_MC4_STATUS 0x00000411
3496#define MSR_IA32_MC5_STATUS 0x00000415
3497#define MSR_IA32_MC6_STATUS 0x00000419
3498#define MSR_IA32_MC7_STATUS 0x0000041D
3499#define MSR_IA32_MC8_STATUS 0x00000421
3500#define MSR_IA32_MC9_STATUS 0x00000425
3501#define MSR_IA32_MC10_STATUS 0x00000429
3502#define MSR_IA32_MC11_STATUS 0x0000042D
3503#define MSR_IA32_MC12_STATUS 0x00000431
3504#define MSR_IA32_MC13_STATUS 0x00000435
3505#define MSR_IA32_MC14_STATUS 0x00000439
3506#define MSR_IA32_MC15_STATUS 0x0000043D
3507#define MSR_IA32_MC16_STATUS 0x00000441
3508#define MSR_IA32_MC17_STATUS 0x00000445
3509#define MSR_IA32_MC18_STATUS 0x00000449
3510#define MSR_IA32_MC19_STATUS 0x0000044D
3511#define MSR_IA32_MC20_STATUS 0x00000451
3512#define MSR_IA32_MC21_STATUS 0x00000455
3513#define MSR_IA32_MC22_STATUS 0x00000459
3514#define MSR_IA32_MC23_STATUS 0x0000045D
3515#define MSR_IA32_MC24_STATUS 0x00000461
3516#define MSR_IA32_MC25_STATUS 0x00000465
3517#define MSR_IA32_MC26_STATUS 0x00000469
3518#define MSR_IA32_MC27_STATUS 0x0000046D
3519#define MSR_IA32_MC28_STATUS 0x00000471
3521
3567#define MSR_IA32_MC0_ADDR 0x00000402
3568#define MSR_IA32_MC1_ADDR 0x00000406
3569#define MSR_IA32_MC2_ADDR 0x0000040A
3570#define MSR_IA32_MC3_ADDR 0x0000040E
3571#define MSR_IA32_MC4_ADDR 0x00000412
3572#define MSR_IA32_MC5_ADDR 0x00000416
3573#define MSR_IA32_MC6_ADDR 0x0000041A
3574#define MSR_IA32_MC7_ADDR 0x0000041E
3575#define MSR_IA32_MC8_ADDR 0x00000422
3576#define MSR_IA32_MC9_ADDR 0x00000426
3577#define MSR_IA32_MC10_ADDR 0x0000042A
3578#define MSR_IA32_MC11_ADDR 0x0000042E
3579#define MSR_IA32_MC12_ADDR 0x00000432
3580#define MSR_IA32_MC13_ADDR 0x00000436
3581#define MSR_IA32_MC14_ADDR 0x0000043A
3582#define MSR_IA32_MC15_ADDR 0x0000043E
3583#define MSR_IA32_MC16_ADDR 0x00000442
3584#define MSR_IA32_MC17_ADDR 0x00000446
3585#define MSR_IA32_MC18_ADDR 0x0000044A
3586#define MSR_IA32_MC19_ADDR 0x0000044E
3587#define MSR_IA32_MC20_ADDR 0x00000452
3588#define MSR_IA32_MC21_ADDR 0x00000456
3589#define MSR_IA32_MC22_ADDR 0x0000045A
3590#define MSR_IA32_MC23_ADDR 0x0000045E
3591#define MSR_IA32_MC24_ADDR 0x00000462
3592#define MSR_IA32_MC25_ADDR 0x00000466
3593#define MSR_IA32_MC26_ADDR 0x0000046A
3594#define MSR_IA32_MC27_ADDR 0x0000046E
3595#define MSR_IA32_MC28_ADDR 0x00000472
3597
3643#define MSR_IA32_MC0_MISC 0x00000403
3644#define MSR_IA32_MC1_MISC 0x00000407
3645#define MSR_IA32_MC2_MISC 0x0000040B
3646#define MSR_IA32_MC3_MISC 0x0000040F
3647#define MSR_IA32_MC4_MISC 0x00000413
3648#define MSR_IA32_MC5_MISC 0x00000417
3649#define MSR_IA32_MC6_MISC 0x0000041B
3650#define MSR_IA32_MC7_MISC 0x0000041F
3651#define MSR_IA32_MC8_MISC 0x00000423
3652#define MSR_IA32_MC9_MISC 0x00000427
3653#define MSR_IA32_MC10_MISC 0x0000042B
3654#define MSR_IA32_MC11_MISC 0x0000042F
3655#define MSR_IA32_MC12_MISC 0x00000433
3656#define MSR_IA32_MC13_MISC 0x00000437
3657#define MSR_IA32_MC14_MISC 0x0000043B
3658#define MSR_IA32_MC15_MISC 0x0000043F
3659#define MSR_IA32_MC16_MISC 0x00000443
3660#define MSR_IA32_MC17_MISC 0x00000447
3661#define MSR_IA32_MC18_MISC 0x0000044B
3662#define MSR_IA32_MC19_MISC 0x0000044F
3663#define MSR_IA32_MC20_MISC 0x00000453
3664#define MSR_IA32_MC21_MISC 0x00000457
3665#define MSR_IA32_MC22_MISC 0x0000045B
3666#define MSR_IA32_MC23_MISC 0x0000045F
3667#define MSR_IA32_MC24_MISC 0x00000463
3668#define MSR_IA32_MC25_MISC 0x00000467
3669#define MSR_IA32_MC26_MISC 0x0000046B
3670#define MSR_IA32_MC27_MISC 0x0000046F
3671#define MSR_IA32_MC28_MISC 0x00000473
3673
3690#define MSR_IA32_VMX_BASIC 0x00000480
3691
3695typedef union {
3699 struct {
3710 UINT32 VmcsRevisonId : 31;
3711 UINT32 MustBeZero : 1;
3717 UINT32 VmcsSize : 13;
3718 UINT32 Reserved1 : 3;
3737 UINT32 DualMonitor : 1;
3763 UINT32 MemoryType : 4;
3779 UINT32 VmxControls : 1;
3780 UINT32 Reserved2 : 8;
3781 } Bits;
3785 UINT64 Uint64;
3787
3791#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00
3792#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06
3796
3813#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
3814
3832#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
3833
3850#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
3851
3868#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
3869
3886#define MSR_IA32_VMX_MISC 0x00000485
3887
3891typedef union {
3895 struct {
3902 UINT32 VmxTimerRatio : 5;
3909 UINT32 VmExitEferLma : 1;
3922 UINT32 Reserved1 : 5;
3973 UINT32 Reserved2 : 1;
3979 } Bits;
3983 UINT64 Uint64;
3985
4002#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
4003
4020#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
4021
4038#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
4039
4056#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
4057
4074#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
4075
4093#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
4094
4112#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
4113
4131#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
4132
4150#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
4151
4168#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
4169
4186#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
4187
4204#define MSR_IA32_VMX_VMFUNC 0x00000491
4205
4231#define MSR_IA32_A_PMC0 0x000004C1
4232#define MSR_IA32_A_PMC1 0x000004C2
4233#define MSR_IA32_A_PMC2 0x000004C3
4234#define MSR_IA32_A_PMC3 0x000004C4
4235#define MSR_IA32_A_PMC4 0x000004C5
4236#define MSR_IA32_A_PMC5 0x000004C6
4237#define MSR_IA32_A_PMC6 0x000004C7
4238#define MSR_IA32_A_PMC7 0x000004C8
4240
4259#define MSR_IA32_MCG_EXT_CTL 0x000004D0
4260
4264typedef union {
4268 struct {
4272 UINT32 LMCE_EN : 1;
4273 UINT32 Reserved1 : 31;
4274 UINT32 Reserved2 : 32;
4275 } Bits;
4279 UINT32 Uint32;
4283 UINT64 Uint64;
4285
4304#define MSR_IA32_SGX_SVN_STATUS 0x00000500
4305
4309typedef union {
4313 struct {
4318 UINT32 Lock : 1;
4319 UINT32 Reserved1 : 15;
4324 UINT32 SGX_SVN_SINIT : 8;
4325 UINT32 Reserved2 : 8;
4326 UINT32 Reserved3 : 32;
4327 } Bits;
4331 UINT32 Uint32;
4335 UINT64 Uint64;
4337
4358#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
4359
4363typedef union {
4367 struct {
4368 UINT32 Reserved : 7;
4372 UINT32 Base : 25;
4376 UINT32 BaseHi : 32;
4377 } Bits;
4381 UINT64 Uint64;
4383
4404#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
4405
4409typedef union {
4413 struct {
4414 UINT32 Reserved : 7;
4422 UINT32 OutputOffset : 32;
4423 } Bits;
4427 UINT64 Uint64;
4429
4433typedef union {
4437 struct {
4441 UINT32 END : 1;
4442 UINT32 Reserved1 : 1;
4446 UINT32 INT : 1;
4447 UINT32 Reserved2 : 1;
4451 UINT32 STOP : 1;
4452 UINT32 Reserved3 : 1;
4457 UINT32 Size : 4;
4458 UINT32 Reserved4 : 2;
4468 UINT32 Base : 20;
4478 UINT32 BaseHi : 32;
4479 } Bits;
4483 UINT64 Uint64;
4485
4489typedef enum {
4490 RtitTopaMemorySize4K = 0,
4491 RtitTopaMemorySize8K,
4492 RtitTopaMemorySize16K,
4493 RtitTopaMemorySize32K,
4494 RtitTopaMemorySize64K,
4495 RtitTopaMemorySize128K,
4496 RtitTopaMemorySize256K,
4497 RtitTopaMemorySize512K,
4498 RtitTopaMemorySize1M,
4499 RtitTopaMemorySize2M,
4500 RtitTopaMemorySize4M,
4501 RtitTopaMemorySize8M,
4502 RtitTopaMemorySize16M,
4503 RtitTopaMemorySize32M,
4504 RtitTopaMemorySize64M,
4505 RtitTopaMemorySize128M
4507
4526#define MSR_IA32_RTIT_CTL 0x00000570
4527
4531typedef union {
4535 struct {
4539 UINT32 TraceEn : 1;
4543 UINT32 CYCEn : 1;
4547 UINT32 OS : 1;
4551 UINT32 User : 1;
4555 UINT32 PwrEvtEn : 1;
4559 UINT32 FUPonPTW : 1;
4563 UINT32 FabricEn : 1;
4567 UINT32 CR3 : 1;
4571 UINT32 ToPA : 1;
4575 UINT32 MTCEn : 1;
4579 UINT32 TSCEn : 1;
4583 UINT32 DisRETC : 1;
4587 UINT32 PTWEn : 1;
4591 UINT32 BranchEn : 1;
4595 UINT32 MTCFreq : 4;
4596 UINT32 Reserved3 : 1;
4600 UINT32 CYCThresh : 4;
4601 UINT32 Reserved4 : 1;
4605 UINT32 PSBFreq : 4;
4606 UINT32 Reserved5 : 4;
4610 UINT32 ADDR0_CFG : 4;
4614 UINT32 ADDR1_CFG : 4;
4618 UINT32 ADDR2_CFG : 4;
4622 UINT32 ADDR3_CFG : 4;
4623 UINT32 Reserved6 : 16;
4624 } Bits;
4628 UINT64 Uint64;
4630
4649#define MSR_IA32_RTIT_STATUS 0x00000571
4650
4654typedef union {
4658 struct {
4663 UINT32 FilterEn : 1;
4667 UINT32 ContexEn : 1;
4671 UINT32 TriggerEn : 1;
4672 UINT32 Reserved1 : 1;
4676 UINT32 Error : 1;
4680 UINT32 Stopped : 1;
4681 UINT32 Reserved2 : 26;
4685 UINT32 PacketByteCnt : 17;
4686 UINT32 Reserved3 : 15;
4687 } Bits;
4691 UINT64 Uint64;
4693
4713#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
4714
4718typedef union {
4722 struct {
4723 UINT32 Reserved : 5;
4727 UINT32 Cr3 : 27;
4731 UINT32 Cr3Hi : 32;
4732 } Bits;
4736 UINT64 Uint64;
4738
4761#define MSR_IA32_RTIT_ADDR0_A 0x00000580
4762#define MSR_IA32_RTIT_ADDR1_A 0x00000582
4763#define MSR_IA32_RTIT_ADDR2_A 0x00000584
4764#define MSR_IA32_RTIT_ADDR3_A 0x00000586
4766
4789#define MSR_IA32_RTIT_ADDR0_B 0x00000581
4790#define MSR_IA32_RTIT_ADDR1_B 0x00000583
4791#define MSR_IA32_RTIT_ADDR2_B 0x00000585
4792#define MSR_IA32_RTIT_ADDR3_B 0x00000587
4794
4800typedef union {
4804 struct {
4808 UINT32 VirtualAddress : 32;
4812 UINT32 VirtualAddressHi : 16;
4816 UINT32 SignExt_VA : 16;
4817 } Bits;
4821 UINT64 Uint64;
4823
4846#define MSR_IA32_DS_AREA 0x00000600
4847
4865#define MSR_IA32_TSC_DEADLINE 0x000006E0
4866
4885#define MSR_IA32_PM_ENABLE 0x00000770
4886
4890typedef union {
4894 struct {
4899 UINT32 HWP_ENABLE : 1;
4900 UINT32 Reserved1 : 31;
4901 UINT32 Reserved2 : 32;
4902 } Bits;
4906 UINT32 Uint32;
4910 UINT64 Uint64;
4912
4930#define MSR_IA32_HWP_CAPABILITIES 0x00000771
4931
4935typedef union {
4939 struct {
4960 UINT32 Reserved : 32;
4961 } Bits;
4965 UINT32 Uint32;
4969 UINT64 Uint64;
4971
4991#define MSR_IA32_HWP_REQUEST_PKG 0x00000772
4992
4996typedef union {
5000 struct {
5025 UINT32 Activity_Window : 10;
5026 UINT32 Reserved : 22;
5027 } Bits;
5031 UINT64 Uint64;
5033
5052#define MSR_IA32_HWP_INTERRUPT 0x00000773
5053
5057typedef union {
5061 struct {
5072 UINT32 Reserved1 : 30;
5073 UINT32 Reserved2 : 32;
5074 } Bits;
5078 UINT32 Uint32;
5082 UINT64 Uint64;
5084
5104#define MSR_IA32_HWP_REQUEST 0x00000774
5105
5109typedef union {
5113 struct {
5138 UINT32 Activity_Window : 10;
5144 UINT32 Reserved : 21;
5145 } Bits;
5149 UINT64 Uint64;
5151
5171#define MSR_IA32_HWP_STATUS 0x00000777
5172
5176typedef union {
5180 struct {
5186 UINT32 Reserved1 : 1;
5192 UINT32 Reserved2 : 29;
5193 UINT32 Reserved3 : 32;
5194 } Bits;
5198 UINT32 Uint32;
5202 UINT64 Uint64;
5204
5221#define MSR_IA32_X2APIC_APICID 0x00000802
5222
5239#define MSR_IA32_X2APIC_VERSION 0x00000803
5240
5258#define MSR_IA32_X2APIC_TPR 0x00000808
5259
5276#define MSR_IA32_X2APIC_PPR 0x0000080A
5277
5295#define MSR_IA32_X2APIC_EOI 0x0000080B
5296
5313#define MSR_IA32_X2APIC_LDR 0x0000080D
5314
5332#define MSR_IA32_X2APIC_SIVR 0x0000080F
5333
5358#define MSR_IA32_X2APIC_ISR0 0x00000810
5359#define MSR_IA32_X2APIC_ISR1 0x00000811
5360#define MSR_IA32_X2APIC_ISR2 0x00000812
5361#define MSR_IA32_X2APIC_ISR3 0x00000813
5362#define MSR_IA32_X2APIC_ISR4 0x00000814
5363#define MSR_IA32_X2APIC_ISR5 0x00000815
5364#define MSR_IA32_X2APIC_ISR6 0x00000816
5365#define MSR_IA32_X2APIC_ISR7 0x00000817
5367
5392#define MSR_IA32_X2APIC_TMR0 0x00000818
5393#define MSR_IA32_X2APIC_TMR1 0x00000819
5394#define MSR_IA32_X2APIC_TMR2 0x0000081A
5395#define MSR_IA32_X2APIC_TMR3 0x0000081B
5396#define MSR_IA32_X2APIC_TMR4 0x0000081C
5397#define MSR_IA32_X2APIC_TMR5 0x0000081D
5398#define MSR_IA32_X2APIC_TMR6 0x0000081E
5399#define MSR_IA32_X2APIC_TMR7 0x0000081F
5401
5426#define MSR_IA32_X2APIC_IRR0 0x00000820
5427#define MSR_IA32_X2APIC_IRR1 0x00000821
5428#define MSR_IA32_X2APIC_IRR2 0x00000822
5429#define MSR_IA32_X2APIC_IRR3 0x00000823
5430#define MSR_IA32_X2APIC_IRR4 0x00000824
5431#define MSR_IA32_X2APIC_IRR5 0x00000825
5432#define MSR_IA32_X2APIC_IRR6 0x00000826
5433#define MSR_IA32_X2APIC_IRR7 0x00000827
5435
5453#define MSR_IA32_X2APIC_ESR 0x00000828
5454
5472#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
5473
5491#define MSR_IA32_X2APIC_ICR 0x00000830
5492
5510#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
5511
5529#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
5530
5548#define MSR_IA32_X2APIC_LVT_PMI 0x00000834
5549
5567#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
5568
5586#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
5587
5605#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
5606
5624#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
5625
5642#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
5643
5661#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
5662
5680#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
5681
5700#define MSR_IA32_DEBUG_INTERFACE 0x00000C80
5701
5705typedef union {
5709 struct {
5714 UINT32 Enable : 1;
5715 UINT32 Reserved1 : 29;
5721 UINT32 Lock : 1;
5726 UINT32 DebugOccurred : 1;
5727 UINT32 Reserved2 : 32;
5728 } Bits;
5732 UINT32 Uint32;
5736 UINT64 Uint64;
5738
5757#define MSR_IA32_L3_QOS_CFG 0x00000C81
5758
5762typedef union {
5766 struct {
5771 UINT32 Enable : 1;
5772 UINT32 Reserved1 : 31;
5773 UINT32 Reserved2 : 32;
5774 } Bits;
5778 UINT32 Uint32;
5782 UINT64 Uint64;
5784
5803#define MSR_IA32_L2_QOS_CFG 0x00000C82
5804
5808typedef union {
5812 struct {
5817 UINT32 Enable : 1;
5818 UINT32 Reserved1 : 31;
5819 UINT32 Reserved2 : 32;
5820 } Bits;
5824 UINT32 Uint32;
5828 UINT64 Uint64;
5830
5850#define MSR_IA32_QM_EVTSEL 0x00000C8D
5851
5855typedef union {
5859 struct {
5864 UINT32 EventID : 8;
5865 UINT32 Reserved : 24;
5872 } Bits;
5876 UINT64 Uint64;
5878
5897#define MSR_IA32_QM_CTR 0x00000C8E
5898
5902typedef union {
5906 struct {
5919 UINT32 Unavailable : 1;
5924 UINT32 Error : 1;
5925 } Bits;
5929 UINT64 Uint64;
5931
5951#define MSR_IA32_PQR_ASSOC 0x00000C8F
5952
5956typedef union {
5960 struct {
5972 UINT32 COS : 32;
5973 } Bits;
5977 UINT64 Uint64;
5979
5999#define MSR_IA32_BNDCFGS 0x00000D90
6000
6004typedef union {
6008 struct {
6012 UINT32 EN : 1;
6017 UINT32 BNDPRESERVE : 1;
6018 UINT32 Reserved : 10;
6022 UINT32 Base : 20;
6026 UINT32 BaseHi : 32;
6027 } Bits;
6031 UINT64 Uint64;
6033
6052#define MSR_IA32_XSS 0x00000DA0
6053
6057typedef union {
6061 struct {
6062 UINT32 Reserved1 : 8;
6067 UINT32 Reserved2 : 23;
6068 UINT32 Reserved3 : 32;
6069 } Bits;
6073 UINT32 Uint32;
6077 UINT64 Uint64;
6079
6098#define MSR_IA32_PKG_HDC_CTL 0x00000DB0
6099
6103typedef union {
6107 struct {
6113 UINT32 HDC_Pkg_Enable : 1;
6114 UINT32 Reserved1 : 31;
6115 UINT32 Reserved2 : 32;
6116 } Bits;
6120 UINT32 Uint32;
6124 UINT64 Uint64;
6126
6145#define MSR_IA32_PM_CTL1 0x00000DB1
6146
6150typedef union {
6154 struct {
6161 UINT32 Reserved1 : 31;
6162 UINT32 Reserved2 : 32;
6163 } Bits;
6167 UINT32 Uint32;
6171 UINT64 Uint64;
6173
6191#define MSR_IA32_THREAD_STALL 0x00000DB2
6192
6212#define MSR_IA32_EFER 0xC0000080
6213
6217typedef union {
6221 struct {
6226 UINT32 SCE : 1;
6227 UINT32 Reserved1 : 7;
6232 UINT32 LME : 1;
6233 UINT32 Reserved2 : 1;
6238 UINT32 LMA : 1;
6242 UINT32 NXE : 1;
6243 UINT32 Reserved3 : 20;
6244 UINT32 Reserved4 : 32;
6245 } Bits;
6249 UINT32 Uint32;
6253 UINT64 Uint64;
6255
6272#define MSR_IA32_STAR 0xC0000081
6273
6290#define MSR_IA32_LSTAR 0xC0000082
6291
6310#define MSR_IA32_CSTAR 0xC0000083
6311
6328#define MSR_IA32_FMASK 0xC0000084
6329
6346#define MSR_IA32_FS_BASE 0xC0000100
6347
6364#define MSR_IA32_GS_BASE 0xC0000101
6365
6382#define MSR_IA32_KERNEL_GS_BASE 0xC0000102
6383
6402#define MSR_IA32_TSC_AUX 0xC0000103
6403
6407typedef union {
6411 struct {
6415 UINT32 AUX : 32;
6416 UINT32 Reserved : 32;
6417 } Bits;
6421 UINT32 Uint32;
6425 UINT64 Uint64;
6427
6428#endif
RTIT_TOPA_MEMORY_SIZE
UINT32 MsegHeaderRevision
UINT32 MonitorFeatures