ArchitecturalMsr.h

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#ifndef __INTEL_ARCHITECTURAL_MSR_H__
#define __INTEL_ARCHITECTURAL_MSR_H__
 
#define MSR_IA32_P5_MC_ADDR  0x00000000
 
#define MSR_IA32_P5_MC_TYPE  0x00000001
 
#define MSR_IA32_MONITOR_FILTER_SIZE  0x00000006
 
#define MSR_IA32_TIME_STAMP_COUNTER  0x00000010
 
#define MSR_IA32_PLATFORM_ID  0x00000017
 
typedef union {
  struct {
    UINT32    Reserved1 : 32;
    UINT32    Reserved2 : 18;
    UINT32    PlatformId : 3;
    UINT32    Reserved3  : 11;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_PLATFORM_ID_REGISTER;
 
#define MSR_IA32_APIC_BASE  0x0000001B
 
typedef union {
  struct {
    UINT32    Reserved1  : 8;
    UINT32    BSP        : 1;
    UINT32    Reserved2  : 1;
    UINT32    EXTD       : 1;
    UINT32    EN         : 1;
    UINT32    ApicBase   : 20;
    UINT32    ApicBaseHi : 32;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_APIC_BASE_REGISTER;
 
#define MSR_IA32_FEATURE_CONTROL  0x0000003A
 
typedef union {
  struct {
    UINT32    Lock : 1;
    UINT32    EnableVmxInsideSmx         : 1;
    UINT32    EnableVmxOutsideSmx        : 1;
    UINT32    Reserved1                  : 5;
    UINT32    SenterLocalFunctionEnables : 7;
    UINT32    SenterGlobalEnable         : 1;
    UINT32    Reserved2                  : 1;
    UINT32    SgxLaunchControlEnable     : 1;
    UINT32    SgxEnable                  : 1;
    UINT32    Reserved3                  : 1;
    UINT32    LmceOn                     : 1;
    UINT32    Reserved4                  : 11;
    UINT32    Reserved5                  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_FEATURE_CONTROL_REGISTER;
 
#define MSR_IA32_TSC_ADJUST  0x0000003B
 
#define MSR_IA32_BIOS_UPDT_TRIG  0x00000079
 
#define MSR_IA32_BIOS_SIGN_ID  0x0000008B
 
typedef union {
  struct {
    UINT32    Reserved : 32;
    UINT32    MicrocodeUpdateSignature : 32;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_BIOS_SIGN_ID_REGISTER;
 
#define MSR_IA32_SGXLEPUBKEYHASH0  0x0000008C
#define MSR_IA32_SGXLEPUBKEYHASH1  0x0000008D
#define MSR_IA32_SGXLEPUBKEYHASH2  0x0000008E
#define MSR_IA32_SGXLEPUBKEYHASH3  0x0000008F
 
#define MSR_IA32_SMM_MONITOR_CTL  0x0000009B
 
typedef union {
  struct {
    UINT32    Valid     : 1;
    UINT32    Reserved1 : 1;
    UINT32    BlockSmi  : 1;
    UINT32    Reserved2 : 9;
    UINT32    MsegBase  : 20;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_SMM_MONITOR_CTL_REGISTER;
 
typedef struct {
  //
  UINT32    MsegHeaderRevision;
  UINT32    MonitorFeatures;
  UINT32    GdtrLimit;
  UINT32    GdtrBaseOffset;
  UINT32    CsSelector;
  UINT32    EipOffset;
  UINT32    EspOffset;
  UINT32    Cr3Offset;
  UINT8     Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
} MSEG_HEADER;
 
#define STM_FEATURES_IA32E  0x1
 
#define MSR_IA32_SMBASE  0x0000009E
 
#define MSR_IA32_PMC0  0x000000C1
#define MSR_IA32_PMC1  0x000000C2
#define MSR_IA32_PMC2  0x000000C3
#define MSR_IA32_PMC3  0x000000C4
#define MSR_IA32_PMC4  0x000000C5
#define MSR_IA32_PMC5  0x000000C6
#define MSR_IA32_PMC6  0x000000C7
#define MSR_IA32_PMC7  0x000000C8
 
#define MSR_IA32_MPERF  0x000000E7
 
#define MSR_IA32_APERF  0x000000E8
 
#define MSR_IA32_MTRRCAP  0x000000FE
 
typedef union {
  struct {
    UINT32    VCNT      : 8;
    UINT32    FIX       : 1;
    UINT32    Reserved1 : 1;
    UINT32    WC        : 1;
    UINT32    SMRR      : 1;
    UINT32    Reserved2 : 20;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_MTRRCAP_REGISTER;
 
#define MSR_IA32_SYSENTER_CS  0x00000174
 
typedef union {
  struct {
    UINT32    CS        : 16;
    UINT32    Reserved1 : 16;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_SYSENTER_CS_REGISTER;
 
#define MSR_IA32_SYSENTER_ESP  0x00000175
 
#define MSR_IA32_SYSENTER_EIP  0x00000176
 
#define MSR_IA32_MCG_CAP  0x00000179
 
typedef union {
  struct {
    UINT32    Count       : 8;
    UINT32    MCG_CTL_P   : 1;
    UINT32    MCG_EXT_P   : 1;
    UINT32    MCP_CMCI_P  : 1;
    UINT32    MCG_TES_P   : 1;
    UINT32    Reserved1   : 4;
    UINT32    MCG_EXT_CNT : 8;
    UINT32    MCG_SER_P   : 1;
    UINT32    Reserved2   : 1;
    UINT32    MCG_ELOG_P : 1;
    UINT32    MCG_LMCE_P : 1;
    UINT32    Reserved3  : 4;
    UINT32    Reserved4  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_MCG_CAP_REGISTER;
 
#define MSR_IA32_MCG_STATUS  0x0000017A
 
typedef union {
  struct {
    UINT32    RIPV      : 1;
    UINT32    EIPV      : 1;
    UINT32    MCIP      : 1;
    UINT32    LMCE_S    : 1;
    UINT32    Reserved1 : 28;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_MCG_STATUS_REGISTER;
 
#define MSR_IA32_MCG_CTL  0x0000017B
 
#define MSR_IA32_PERFEVTSEL0  0x00000186
#define MSR_IA32_PERFEVTSEL1  0x00000187
#define MSR_IA32_PERFEVTSEL2  0x00000188
#define MSR_IA32_PERFEVTSEL3  0x00000189
 
typedef union {
  struct {
    UINT32    EventSelect : 8;
    UINT32    UMASK       : 8;
    UINT32    USR         : 1;
    UINT32    OS          : 1;
    UINT32    E           : 1;
    UINT32    PC          : 1;
    UINT32    INT         : 1;
    UINT32    ANY         : 1;
    UINT32    EN          : 1;
    UINT32    INV         : 1;
    UINT32    CMASK       : 8;
    UINT32    Reserved    : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_PERFEVTSEL_REGISTER;
 
#define MSR_IA32_PERF_STATUS  0x00000198
 
typedef union {
  struct {
    UINT32    State     : 16;
    UINT32    Reserved1 : 16;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_PERF_STATUS_REGISTER;
 
#define MSR_IA32_PERF_CTL  0x00000199
 
typedef union {
  struct {
    UINT32    TargetState : 16;
    UINT32    Reserved1   : 16;
    UINT32    IDA         : 1;
    UINT32    Reserved2   : 31;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_PERF_CTL_REGISTER;
 
#define MSR_IA32_CLOCK_MODULATION  0x0000019A
 
typedef union {
  struct {
    UINT32    ExtendedOnDemandClockModulationDutyCycle : 1;
    UINT32    OnDemandClockModulationDutyCycle         : 3;
    UINT32    OnDemandClockModulationEnable            : 1;
    UINT32    Reserved1                                : 27;
    UINT32    Reserved2                                : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_CLOCK_MODULATION_REGISTER;
 
#define MSR_IA32_THERM_INTERRUPT  0x0000019B
 
typedef union {
  struct {
    UINT32    HighTempEnable               : 1;
    UINT32    LowTempEnable                : 1;
    UINT32    PROCHOT_Enable               : 1;
    UINT32    FORCEPR_Enable               : 1;
    UINT32    CriticalTempEnable           : 1;
    UINT32    Reserved1                    : 3;
    UINT32    Threshold1                   : 7;
    UINT32    Threshold1Enable             : 1;
    UINT32    Threshold2                   : 7;
    UINT32    Threshold2Enable             : 1;
    UINT32    PowerLimitNotificationEnable : 1;
    UINT32    Reserved2                    : 7;
    UINT32    Reserved3                    : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_THERM_INTERRUPT_REGISTER;
 
#define MSR_IA32_THERM_STATUS  0x0000019C
 
typedef union {
  struct {
    UINT32    ThermalStatus              : 1;
    UINT32    ThermalStatusLog           : 1;
    UINT32    PROCHOT_FORCEPR_Event      : 1;
    UINT32    PROCHOT_FORCEPR_Log        : 1;
    UINT32    CriticalTempStatus         : 1;
    UINT32    CriticalTempStatusLog      : 1;
    UINT32    ThermalThreshold1Status    : 1;
    UINT32    ThermalThreshold1Log       : 1;
    UINT32    ThermalThreshold2Status    : 1;
    UINT32    ThermalThreshold2Log       : 1;
    UINT32    PowerLimitStatus           : 1;
    UINT32    PowerLimitLog              : 1;
    UINT32    CurrentLimitStatus         : 1;
    UINT32    CurrentLimitLog            : 1;
    UINT32    CrossDomainLimitStatus     : 1;
    UINT32    CrossDomainLimitLog        : 1;
    UINT32    DigitalReadout             : 7;
    UINT32    Reserved1                  : 4;
    UINT32    ResolutionInDegreesCelsius : 4;
    UINT32    ReadingValid               : 1;
    UINT32    Reserved2                  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_THERM_STATUS_REGISTER;
 
#define MSR_IA32_MISC_ENABLE  0x000001A0
 
typedef union {
  struct {
    UINT32    FastStrings : 1;
    UINT32    Reserved1   : 2;
    UINT32    AutomaticThermalControlCircuit : 1;
    UINT32    Reserved2                      : 3;
    UINT32    PerformanceMonitoring          : 1;
    UINT32    Reserved3                      : 3;
    UINT32    BTS                            : 1;
    UINT32    PEBS                           : 1;
    UINT32    Reserved4                      : 3;
    UINT32    EIST                           : 1;
    UINT32    Reserved5                      : 1;
    UINT32    MONITOR   : 1;
    UINT32    Reserved6 : 3;
    UINT32    LimitCpuidMaxval     : 1;
    UINT32    xTPR_Message_Disable : 1;
    UINT32    Reserved7            : 8;
    UINT32    Reserved8            : 2;
    UINT32    XD        : 1;
    UINT32    Reserved9 : 29;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_MISC_ENABLE_REGISTER;
 
#define MSR_IA32_ENERGY_PERF_BIAS  0x000001B0
 
typedef union {
  struct {
    UINT32    PowerPolicyPreference : 4;
    UINT32    Reserved1             : 28;
    UINT32    Reserved2             : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_ENERGY_PERF_BIAS_REGISTER;
 
#define MSR_IA32_PACKAGE_THERM_STATUS  0x000001B1
 
typedef union {
  struct {
    UINT32    ThermalStatus           : 1;
    UINT32    ThermalStatusLog        : 1;
    UINT32    PROCHOT_Event           : 1;
    UINT32    PROCHOT_Log             : 1;
    UINT32    CriticalTempStatus      : 1;
    UINT32    CriticalTempStatusLog   : 1;
    UINT32    ThermalThreshold1Status : 1;
    UINT32    ThermalThreshold1Log    : 1;
    UINT32    ThermalThreshold2Status : 1;
    UINT32    ThermalThreshold2Log    : 1;
    UINT32    PowerLimitStatus        : 1;
    UINT32    PowerLimitLog           : 1;
    UINT32    Reserved1               : 4;
    UINT32    DigitalReadout          : 7;
    UINT32    Reserved2               : 9;
    UINT32    Reserved3               : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;
 
#define MSR_IA32_PACKAGE_THERM_INTERRUPT  0x000001B2
 
typedef union {
  struct {
    UINT32    HighTempEnable               : 1;
    UINT32    LowTempEnable                : 1;
    UINT32    PROCHOT_Enable               : 1;
    UINT32    Reserved1                    : 1;
    UINT32    OverheatEnable               : 1;
    UINT32    Reserved2                    : 3;
    UINT32    Threshold1                   : 7;
    UINT32    Threshold1Enable             : 1;
    UINT32    Threshold2                   : 7;
    UINT32    Threshold2Enable             : 1;
    UINT32    PowerLimitNotificationEnable : 1;
    UINT32    Reserved3                    : 7;
    UINT32    Reserved4                    : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;
 
#define MSR_IA32_DEBUGCTL  0x000001D9
 
typedef union {
  struct {
    UINT32    LBR                   : 1;
    UINT32    BTF                   : 1;
    UINT32    Reserved1             : 4;
    UINT32    TR                    : 1;
    UINT32    BTS                   : 1;
    UINT32    BTINT                 : 1;
    UINT32    BTS_OFF_OS            : 1;
    UINT32    BTS_OFF_USR           : 1;
    UINT32    FREEZE_LBRS_ON_PMI    : 1;
    UINT32    FREEZE_PERFMON_ON_PMI : 1;
    UINT32    ENABLE_UNCORE_PMI     : 1;
    UINT32    FREEZE_WHILE_SMM      : 1;
    UINT32    RTM_DEBUG             : 1;
    UINT32    Reserved2             : 16;
    UINT32    Reserved3             : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_DEBUGCTL_REGISTER;
 
#define MSR_IA32_SMRR_PHYSBASE  0x000001F2
 
typedef union {
  struct {
    UINT32    Type      : 8;
    UINT32    Reserved1 : 4;
    UINT32    PhysBase  : 20;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_SMRR_PHYSBASE_REGISTER;
 
#define MSR_IA32_SMRR_PHYSMASK  0x000001F3
 
typedef union {
  struct {
    UINT32    Reserved1 : 11;
    UINT32    Valid     : 1;
    UINT32    PhysMask  : 20;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_SMRR_PHYSMASK_REGISTER;
 
#define MSR_IA32_PLATFORM_DCA_CAP  0x000001F8
 
#define MSR_IA32_CPU_DCA_CAP  0x000001F9
 
#define MSR_IA32_DCA_0_CAP  0x000001FA
 
typedef union {
  struct {
    UINT32    DCA_ACTIVE     : 1;
    UINT32    TRANSACTION    : 2;
    UINT32    DCA_TYPE       : 4;
    UINT32    DCA_QUEUE_SIZE : 4;
    UINT32    Reserved1      : 2;
    UINT32    DCA_DELAY      : 4;
    UINT32    Reserved2      : 7;
    UINT32    SW_BLOCK       : 1;
    UINT32    Reserved3      : 1;
    UINT32    HW_BLOCK       : 1;
    UINT32    Reserved4      : 5;
    UINT32    Reserved5      : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_DCA_0_CAP_REGISTER;
 
#define MSR_IA32_MTRR_PHYSBASE0  0x00000200
#define MSR_IA32_MTRR_PHYSBASE1  0x00000202
#define MSR_IA32_MTRR_PHYSBASE2  0x00000204
#define MSR_IA32_MTRR_PHYSBASE3  0x00000206
#define MSR_IA32_MTRR_PHYSBASE4  0x00000208
#define MSR_IA32_MTRR_PHYSBASE5  0x0000020A
#define MSR_IA32_MTRR_PHYSBASE6  0x0000020C
#define MSR_IA32_MTRR_PHYSBASE7  0x0000020E
#define MSR_IA32_MTRR_PHYSBASE8  0x00000210
#define MSR_IA32_MTRR_PHYSBASE9  0x00000212
 
typedef union {
  struct {
    UINT32    Type      : 8;
    UINT32    Reserved1 : 4;
    UINT32    PhysBase  : 20;
    UINT32    PhysBaseHi : 32;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_MTRR_PHYSBASE_REGISTER;
 
#define MSR_IA32_MTRR_PHYSMASK0  0x00000201
#define MSR_IA32_MTRR_PHYSMASK1  0x00000203
#define MSR_IA32_MTRR_PHYSMASK2  0x00000205
#define MSR_IA32_MTRR_PHYSMASK3  0x00000207
#define MSR_IA32_MTRR_PHYSMASK4  0x00000209
#define MSR_IA32_MTRR_PHYSMASK5  0x0000020B
#define MSR_IA32_MTRR_PHYSMASK6  0x0000020D
#define MSR_IA32_MTRR_PHYSMASK7  0x0000020F
#define MSR_IA32_MTRR_PHYSMASK8  0x00000211
#define MSR_IA32_MTRR_PHYSMASK9  0x00000213
 
typedef union {
  struct {
    UINT32    Reserved1 : 11;
    UINT32    V         : 1;
    UINT32    PhysMask  : 20;
    UINT32    PhysMaskHi : 32;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_MTRR_PHYSMASK_REGISTER;
 
#define MSR_IA32_MTRR_FIX64K_00000  0x00000250
 
#define MSR_IA32_MTRR_FIX16K_80000  0x00000258
 
#define MSR_IA32_MTRR_FIX16K_A0000  0x00000259
 
#define MSR_IA32_MTRR_FIX4K_C0000  0x00000268
 
#define MSR_IA32_MTRR_FIX4K_C8000  0x00000269
 
#define MSR_IA32_MTRR_FIX4K_D0000  0x0000026A
 
#define MSR_IA32_MTRR_FIX4K_D8000  0x0000026B
 
#define MSR_IA32_MTRR_FIX4K_E0000  0x0000026C
 
#define MSR_IA32_MTRR_FIX4K_E8000  0x0000026D
 
#define MSR_IA32_MTRR_FIX4K_F0000  0x0000026E
 
#define MSR_IA32_MTRR_FIX4K_F8000  0x0000026F
 
#define MSR_IA32_PAT  0x00000277
 
typedef union {
  struct {
    UINT32    PA0       : 3;
    UINT32    Reserved1 : 5;
    UINT32    PA1       : 3;
    UINT32    Reserved2 : 5;
    UINT32    PA2       : 3;
    UINT32    Reserved3 : 5;
    UINT32    PA3       : 3;
    UINT32    Reserved4 : 5;
    UINT32    PA4       : 3;
    UINT32    Reserved5 : 5;
    UINT32    PA5       : 3;
    UINT32    Reserved6 : 5;
    UINT32    PA6       : 3;
    UINT32    Reserved7 : 5;
    UINT32    PA7       : 3;
    UINT32    Reserved8 : 5;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_PAT_REGISTER;
 
#define MSR_IA32_MC0_CTL2   0x00000280
#define MSR_IA32_MC1_CTL2   0x00000281
#define MSR_IA32_MC2_CTL2   0x00000282
#define MSR_IA32_MC3_CTL2   0x00000283
#define MSR_IA32_MC4_CTL2   0x00000284
#define MSR_IA32_MC5_CTL2   0x00000285
#define MSR_IA32_MC6_CTL2   0x00000286
#define MSR_IA32_MC7_CTL2   0x00000287
#define MSR_IA32_MC8_CTL2   0x00000288
#define MSR_IA32_MC9_CTL2   0x00000289
#define MSR_IA32_MC10_CTL2  0x0000028A
#define MSR_IA32_MC11_CTL2  0x0000028B
#define MSR_IA32_MC12_CTL2  0x0000028C
#define MSR_IA32_MC13_CTL2  0x0000028D
#define MSR_IA32_MC14_CTL2  0x0000028E
#define MSR_IA32_MC15_CTL2  0x0000028F
#define MSR_IA32_MC16_CTL2  0x00000290
#define MSR_IA32_MC17_CTL2  0x00000291
#define MSR_IA32_MC18_CTL2  0x00000292
#define MSR_IA32_MC19_CTL2  0x00000293
#define MSR_IA32_MC20_CTL2  0x00000294
#define MSR_IA32_MC21_CTL2  0x00000295
#define MSR_IA32_MC22_CTL2  0x00000296
#define MSR_IA32_MC23_CTL2  0x00000297
#define MSR_IA32_MC24_CTL2  0x00000298
#define MSR_IA32_MC25_CTL2  0x00000299
#define MSR_IA32_MC26_CTL2  0x0000029A
#define MSR_IA32_MC27_CTL2  0x0000029B
#define MSR_IA32_MC28_CTL2  0x0000029C
#define MSR_IA32_MC29_CTL2  0x0000029D
#define MSR_IA32_MC30_CTL2  0x0000029E
#define MSR_IA32_MC31_CTL2  0x0000029F
 
typedef union {
  struct {
    UINT32    CorrectedErrorCountThreshold : 15;
    UINT32    Reserved1                    : 15;
    UINT32    CMCI_EN                      : 1;
    UINT32    Reserved2                    : 1;
    UINT32    Reserved3                    : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_MC_CTL2_REGISTER;
 
#define MSR_IA32_MTRR_DEF_TYPE  0x000002FF
 
typedef union {
  struct {
    UINT32    Type      : 3;
    UINT32    Reserved1 : 7;
    UINT32    FE        : 1;
    UINT32    E         : 1;
    UINT32    Reserved2 : 20;
    UINT32    Reserved3 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_MTRR_DEF_TYPE_REGISTER;
 
#define MSR_IA32_FIXED_CTR0  0x00000309
 
#define MSR_IA32_FIXED_CTR1  0x0000030A
 
#define MSR_IA32_FIXED_CTR2  0x0000030B
 
#define MSR_IA32_PERF_CAPABILITIES  0x00000345
 
typedef union {
  struct {
    UINT32    LBR_FMT       : 6;
    UINT32    PEBS_TRAP     : 1;
    UINT32    PEBS_ARCH_REG : 1;
    UINT32    PEBS_REC_FMT  : 4;
    UINT32    SMM_FREEZE    : 1;
    UINT32    FW_WRITE      : 1;
    UINT32    Reserved1     : 18;
    UINT32    Reserved2     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_PERF_CAPABILITIES_REGISTER;
 
#define MSR_IA32_FIXED_CTR_CTRL  0x0000038D
 
typedef union {
  struct {
    UINT32    EN0_OS     : 1;
    UINT32    EN0_Usr    : 1;
    UINT32    AnyThread0 : 1;
    UINT32    EN0_PMI    : 1;
    UINT32    EN1_OS     : 1;
    UINT32    EN1_Usr    : 1;
    UINT32    AnyThread1 : 1;
    UINT32    EN1_PMI    : 1;
    UINT32    EN2_OS     : 1;
    UINT32    EN2_Usr    : 1;
    UINT32    AnyThread2 : 1;
    UINT32    EN2_PMI    : 1;
    UINT32    Reserved1  : 20;
    UINT32    Reserved2  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_FIXED_CTR_CTRL_REGISTER;
 
#define MSR_IA32_PERF_GLOBAL_STATUS  0x0000038E
 
typedef union {
  struct {
    UINT32    Ovf_PMC0       : 1;
    UINT32    Ovf_PMC1       : 1;
    UINT32    Ovf_PMC2       : 1;
    UINT32    Ovf_PMC3       : 1;
    UINT32    Reserved1      : 28;
    UINT32    Ovf_FixedCtr0  : 1;
    UINT32    Ovf_FixedCtr1  : 1;
    UINT32    Ovf_FixedCtr2  : 1;
    UINT32    Reserved2      : 20;
    UINT32    Trace_ToPA_PMI : 1;
    UINT32    Reserved3      : 2;
    UINT32    LBR_Frz        : 1;
    UINT32    CTR_Frz        : 1;
    UINT32    ASCI           : 1;
    UINT32    Ovf_Uncore     : 1;
    UINT32    OvfBuf         : 1;
    UINT32    CondChgd       : 1;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;
 
#define MSR_IA32_PERF_GLOBAL_CTRL  0x0000038F
 
typedef union {
  struct {
    UINT32    EN_PMCn       : 32;
    UINT32    EN_FIXED_CTRn : 32;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;
 
#define MSR_IA32_PERF_GLOBAL_OVF_CTRL  0x00000390
 
typedef union {
  struct {
    UINT32    Ovf_PMCn       : 32;
    UINT32    Ovf_FIXED_CTRn : 23;
    UINT32    Trace_ToPA_PMI : 1;
    UINT32    Reserved2      : 5;
    UINT32    Ovf_Uncore     : 1;
    UINT32    OvfBuf         : 1;
    UINT32    CondChgd       : 1;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;
 
#define MSR_IA32_PERF_GLOBAL_STATUS_RESET  0x00000390
 
typedef union {
  struct {
    UINT32    Ovf_PMCn       : 32;
    UINT32    Ovf_FIXED_CTRn : 23;
    UINT32    Trace_ToPA_PMI : 1;
    UINT32    Reserved2      : 2;
    UINT32    LBR_Frz        : 1;
    UINT32    CTR_Frz        : 1;
    UINT32    ASCI           : 1;
    UINT32    Ovf_Uncore     : 1;
    UINT32    OvfBuf         : 1;
    UINT32    CondChgd       : 1;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
 
#define MSR_IA32_PERF_GLOBAL_STATUS_SET  0x00000391
 
typedef union {
  struct {
    UINT32    Ovf_PMCn       : 32;
    UINT32    Ovf_FIXED_CTRn : 23;
    UINT32    Trace_ToPA_PMI : 1;
    UINT32    Reserved2      : 2;
    UINT32    LBR_Frz        : 1;
    UINT32    CTR_Frz        : 1;
    UINT32    ASCI           : 1;
    UINT32    Ovf_Uncore     : 1;
    UINT32    OvfBuf         : 1;
    UINT32    Reserved3      : 1;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
 
#define MSR_IA32_PERF_GLOBAL_INUSE  0x00000392
 
typedef union {
  struct {
    UINT32    IA32_PERFEVTSELn : 32;
    UINT32    IA32_FIXED_CTRn  : 31;
    UINT32    PMI              : 1;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;
 
#define MSR_IA32_PEBS_ENABLE  0x000003F1
 
typedef union {
  struct {
    UINT32    Enable    : 1;
    UINT32    Reserved1 : 3;
    UINT32    Reserved2 : 28;
    UINT32    Reserved3 : 4;
    UINT32    Reserved4 : 28;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_PEBS_ENABLE_REGISTER;
 
#define MSR_IA32_MC0_CTL   0x00000400
#define MSR_IA32_MC1_CTL   0x00000404
#define MSR_IA32_MC2_CTL   0x00000408
#define MSR_IA32_MC3_CTL   0x0000040C
#define MSR_IA32_MC4_CTL   0x00000410
#define MSR_IA32_MC5_CTL   0x00000414
#define MSR_IA32_MC6_CTL   0x00000418
#define MSR_IA32_MC7_CTL   0x0000041C
#define MSR_IA32_MC8_CTL   0x00000420
#define MSR_IA32_MC9_CTL   0x00000424
#define MSR_IA32_MC10_CTL  0x00000428
#define MSR_IA32_MC11_CTL  0x0000042C
#define MSR_IA32_MC12_CTL  0x00000430
#define MSR_IA32_MC13_CTL  0x00000434
#define MSR_IA32_MC14_CTL  0x00000438
#define MSR_IA32_MC15_CTL  0x0000043C
#define MSR_IA32_MC16_CTL  0x00000440
#define MSR_IA32_MC17_CTL  0x00000444
#define MSR_IA32_MC18_CTL  0x00000448
#define MSR_IA32_MC19_CTL  0x0000044C
#define MSR_IA32_MC20_CTL  0x00000450
#define MSR_IA32_MC21_CTL  0x00000454
#define MSR_IA32_MC22_CTL  0x00000458
#define MSR_IA32_MC23_CTL  0x0000045C
#define MSR_IA32_MC24_CTL  0x00000460
#define MSR_IA32_MC25_CTL  0x00000464
#define MSR_IA32_MC26_CTL  0x00000468
#define MSR_IA32_MC27_CTL  0x0000046C
#define MSR_IA32_MC28_CTL  0x00000470
 
#define MSR_IA32_MC0_STATUS   0x00000401
#define MSR_IA32_MC1_STATUS   0x00000405
#define MSR_IA32_MC2_STATUS   0x00000409
#define MSR_IA32_MC3_STATUS   0x0000040D
#define MSR_IA32_MC4_STATUS   0x00000411
#define MSR_IA32_MC5_STATUS   0x00000415
#define MSR_IA32_MC6_STATUS   0x00000419
#define MSR_IA32_MC7_STATUS   0x0000041D
#define MSR_IA32_MC8_STATUS   0x00000421
#define MSR_IA32_MC9_STATUS   0x00000425
#define MSR_IA32_MC10_STATUS  0x00000429
#define MSR_IA32_MC11_STATUS  0x0000042D
#define MSR_IA32_MC12_STATUS  0x00000431
#define MSR_IA32_MC13_STATUS  0x00000435
#define MSR_IA32_MC14_STATUS  0x00000439
#define MSR_IA32_MC15_STATUS  0x0000043D
#define MSR_IA32_MC16_STATUS  0x00000441
#define MSR_IA32_MC17_STATUS  0x00000445
#define MSR_IA32_MC18_STATUS  0x00000449
#define MSR_IA32_MC19_STATUS  0x0000044D
#define MSR_IA32_MC20_STATUS  0x00000451
#define MSR_IA32_MC21_STATUS  0x00000455
#define MSR_IA32_MC22_STATUS  0x00000459
#define MSR_IA32_MC23_STATUS  0x0000045D
#define MSR_IA32_MC24_STATUS  0x00000461
#define MSR_IA32_MC25_STATUS  0x00000465
#define MSR_IA32_MC26_STATUS  0x00000469
#define MSR_IA32_MC27_STATUS  0x0000046D
#define MSR_IA32_MC28_STATUS  0x00000471
 
#define MSR_IA32_MC0_ADDR   0x00000402
#define MSR_IA32_MC1_ADDR   0x00000406
#define MSR_IA32_MC2_ADDR   0x0000040A
#define MSR_IA32_MC3_ADDR   0x0000040E
#define MSR_IA32_MC4_ADDR   0x00000412
#define MSR_IA32_MC5_ADDR   0x00000416
#define MSR_IA32_MC6_ADDR   0x0000041A
#define MSR_IA32_MC7_ADDR   0x0000041E
#define MSR_IA32_MC8_ADDR   0x00000422
#define MSR_IA32_MC9_ADDR   0x00000426
#define MSR_IA32_MC10_ADDR  0x0000042A
#define MSR_IA32_MC11_ADDR  0x0000042E
#define MSR_IA32_MC12_ADDR  0x00000432
#define MSR_IA32_MC13_ADDR  0x00000436
#define MSR_IA32_MC14_ADDR  0x0000043A
#define MSR_IA32_MC15_ADDR  0x0000043E
#define MSR_IA32_MC16_ADDR  0x00000442
#define MSR_IA32_MC17_ADDR  0x00000446
#define MSR_IA32_MC18_ADDR  0x0000044A
#define MSR_IA32_MC19_ADDR  0x0000044E
#define MSR_IA32_MC20_ADDR  0x00000452
#define MSR_IA32_MC21_ADDR  0x00000456
#define MSR_IA32_MC22_ADDR  0x0000045A
#define MSR_IA32_MC23_ADDR  0x0000045E
#define MSR_IA32_MC24_ADDR  0x00000462
#define MSR_IA32_MC25_ADDR  0x00000466
#define MSR_IA32_MC26_ADDR  0x0000046A
#define MSR_IA32_MC27_ADDR  0x0000046E
#define MSR_IA32_MC28_ADDR  0x00000472
 
#define MSR_IA32_MC0_MISC   0x00000403
#define MSR_IA32_MC1_MISC   0x00000407
#define MSR_IA32_MC2_MISC   0x0000040B
#define MSR_IA32_MC3_MISC   0x0000040F
#define MSR_IA32_MC4_MISC   0x00000413
#define MSR_IA32_MC5_MISC   0x00000417
#define MSR_IA32_MC6_MISC   0x0000041B
#define MSR_IA32_MC7_MISC   0x0000041F
#define MSR_IA32_MC8_MISC   0x00000423
#define MSR_IA32_MC9_MISC   0x00000427
#define MSR_IA32_MC10_MISC  0x0000042B
#define MSR_IA32_MC11_MISC  0x0000042F
#define MSR_IA32_MC12_MISC  0x00000433
#define MSR_IA32_MC13_MISC  0x00000437
#define MSR_IA32_MC14_MISC  0x0000043B
#define MSR_IA32_MC15_MISC  0x0000043F
#define MSR_IA32_MC16_MISC  0x00000443
#define MSR_IA32_MC17_MISC  0x00000447
#define MSR_IA32_MC18_MISC  0x0000044B
#define MSR_IA32_MC19_MISC  0x0000044F
#define MSR_IA32_MC20_MISC  0x00000453
#define MSR_IA32_MC21_MISC  0x00000457
#define MSR_IA32_MC22_MISC  0x0000045B
#define MSR_IA32_MC23_MISC  0x0000045F
#define MSR_IA32_MC24_MISC  0x00000463
#define MSR_IA32_MC25_MISC  0x00000467
#define MSR_IA32_MC26_MISC  0x0000046B
#define MSR_IA32_MC27_MISC  0x0000046F
#define MSR_IA32_MC28_MISC  0x00000473
 
#define MSR_IA32_VMX_BASIC  0x00000480
 
typedef union {
  struct {
    UINT32    VmcsRevisonId : 31;
    UINT32    MustBeZero    : 1;
    UINT32    VmcsSize      : 13;
    UINT32    Reserved1     : 3;
    UINT32    VmcsAddressWidth : 1;
    UINT32    DualMonitor      : 1;
    UINT32    MemoryType       : 4;
    UINT32    InsOutsReporting : 1;
    UINT32    VmxControls : 1;
    UINT32    Reserved2   : 8;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_VMX_BASIC_REGISTER;
 
#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE  0x00
#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK   0x06
 
#define MSR_IA32_VMX_PINBASED_CTLS  0x00000481
 
#define MSR_IA32_VMX_PROCBASED_CTLS  0x00000482
 
#define MSR_IA32_VMX_EXIT_CTLS  0x00000483
 
#define MSR_IA32_VMX_ENTRY_CTLS  0x00000484
 
#define MSR_IA32_VMX_MISC  0x00000485
 
typedef union {
  struct {
    UINT32    VmxTimerRatio                     : 5;
    UINT32    VmExitEferLma                     : 1;
    UINT32    HltActivityStateSupported         : 1;
    UINT32    ShutdownActivityStateSupported    : 1;
    UINT32    WaitForSipiActivityStateSupported : 1;
    UINT32    Reserved1                         : 5;
    UINT32    ProcessorTraceSupported : 1;
    UINT32    SmBaseMsrSupported      : 1;
    UINT32    NumberOfCr3TargetValues : 9;
    UINT32    MsrStoreListMaximum    : 3;
    UINT32    BlockSmiSupported      : 1;
    UINT32    VmWriteSupported       : 1;
    UINT32    VmInjectSupported      : 1;
    UINT32    Reserved2              : 1;
    UINT32    MsegRevisionIdentifier : 32;
  } Bits;
  UINT64    Uint64;
} IA32_VMX_MISC_REGISTER;
 
#define MSR_IA32_VMX_CR0_FIXED0  0x00000486
 
#define MSR_IA32_VMX_CR0_FIXED1  0x00000487
 
#define MSR_IA32_VMX_CR4_FIXED0  0x00000488
 
#define MSR_IA32_VMX_CR4_FIXED1  0x00000489
 
#define MSR_IA32_VMX_VMCS_ENUM  0x0000048A
 
#define MSR_IA32_VMX_PROCBASED_CTLS2  0x0000048B
 
#define MSR_IA32_VMX_EPT_VPID_CAP  0x0000048C
 
#define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048D
 
#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS  0x0000048E
 
#define MSR_IA32_VMX_TRUE_EXIT_CTLS  0x0000048F
 
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS  0x00000490
 
#define MSR_IA32_VMX_VMFUNC  0x00000491
 
#define MSR_IA32_A_PMC0  0x000004C1
#define MSR_IA32_A_PMC1  0x000004C2
#define MSR_IA32_A_PMC2  0x000004C3
#define MSR_IA32_A_PMC3  0x000004C4
#define MSR_IA32_A_PMC4  0x000004C5
#define MSR_IA32_A_PMC5  0x000004C6
#define MSR_IA32_A_PMC6  0x000004C7
#define MSR_IA32_A_PMC7  0x000004C8
 
#define MSR_IA32_MCG_EXT_CTL  0x000004D0
 
typedef union {
  struct {
    UINT32    LMCE_EN   : 1;
    UINT32    Reserved1 : 31;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_MCG_EXT_CTL_REGISTER;
 
#define MSR_IA32_SGX_SVN_STATUS  0x00000500
 
typedef union {
  struct {
    UINT32    Lock          : 1;
    UINT32    Reserved1     : 15;
    UINT32    SGX_SVN_SINIT : 8;
    UINT32    Reserved2     : 8;
    UINT32    Reserved3     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_SGX_SVN_STATUS_REGISTER;
 
#define MSR_IA32_RTIT_OUTPUT_BASE  0x00000560
 
typedef union {
  struct {
    UINT32    Reserved : 7;
    UINT32    Base     : 25;
    UINT32    BaseHi   : 32;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;
 
#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS  0x00000561
 
typedef union {
  struct {
    UINT32    Reserved          : 7;
    UINT32    MaskOrTableOffset : 25;
    UINT32    OutputOffset      : 32;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;
 
typedef union {
  struct {
    UINT32    END       : 1;
    UINT32    Reserved1 : 1;
    UINT32    INT       : 1;
    UINT32    Reserved2 : 1;
    UINT32    STOP      : 1;
    UINT32    Reserved3 : 1;
    UINT32    Size      : 4;
    UINT32    Reserved4 : 2;
    UINT32    Base : 20;
    UINT32    BaseHi : 32;
  } Bits;
  UINT64    Uint64;
} RTIT_TOPA_TABLE_ENTRY;
 
typedef enum {
  RtitTopaMemorySize4K = 0,
  RtitTopaMemorySize8K,
  RtitTopaMemorySize16K,
  RtitTopaMemorySize32K,
  RtitTopaMemorySize64K,
  RtitTopaMemorySize128K,
  RtitTopaMemorySize256K,
  RtitTopaMemorySize512K,
  RtitTopaMemorySize1M,
  RtitTopaMemorySize2M,
  RtitTopaMemorySize4M,
  RtitTopaMemorySize8M,
  RtitTopaMemorySize16M,
  RtitTopaMemorySize32M,
  RtitTopaMemorySize64M,
  RtitTopaMemorySize128M
} RTIT_TOPA_MEMORY_SIZE;
 
#define MSR_IA32_RTIT_CTL  0x00000570
 
typedef union {
  struct {
    UINT32    TraceEn   : 1;
    UINT32    CYCEn     : 1;
    UINT32    OS        : 1;
    UINT32    User      : 1;
    UINT32    PwrEvtEn  : 1;
    UINT32    FUPonPTW  : 1;
    UINT32    FabricEn  : 1;
    UINT32    CR3       : 1;
    UINT32    ToPA      : 1;
    UINT32    MTCEn     : 1;
    UINT32    TSCEn     : 1;
    UINT32    DisRETC   : 1;
    UINT32    PTWEn     : 1;
    UINT32    BranchEn  : 1;
    UINT32    MTCFreq   : 4;
    UINT32    Reserved3 : 1;
    UINT32    CYCThresh : 4;
    UINT32    Reserved4 : 1;
    UINT32    PSBFreq   : 4;
    UINT32    Reserved5 : 4;
    UINT32    ADDR0_CFG : 4;
    UINT32    ADDR1_CFG : 4;
    UINT32    ADDR2_CFG : 4;
    UINT32    ADDR3_CFG : 4;
    UINT32    Reserved6 : 16;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_RTIT_CTL_REGISTER;
 
#define MSR_IA32_RTIT_STATUS  0x00000571
 
typedef union {
  struct {
    UINT32    FilterEn      : 1;
    UINT32    ContexEn      : 1;
    UINT32    TriggerEn     : 1;
    UINT32    Reserved1     : 1;
    UINT32    Error         : 1;
    UINT32    Stopped       : 1;
    UINT32    Reserved2     : 26;
    UINT32    PacketByteCnt : 17;
    UINT32    Reserved3     : 15;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_RTIT_STATUS_REGISTER;
 
#define MSR_IA32_RTIT_CR3_MATCH  0x00000572
 
typedef union {
  struct {
    UINT32    Reserved : 5;
    UINT32    Cr3      : 27;
    UINT32    Cr3Hi    : 32;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_RTIT_CR3_MATCH_REGISTER;
 
#define MSR_IA32_RTIT_ADDR0_A  0x00000580
#define MSR_IA32_RTIT_ADDR1_A  0x00000582
#define MSR_IA32_RTIT_ADDR2_A  0x00000584
#define MSR_IA32_RTIT_ADDR3_A  0x00000586
 
#define MSR_IA32_RTIT_ADDR0_B  0x00000581
#define MSR_IA32_RTIT_ADDR1_B  0x00000583
#define MSR_IA32_RTIT_ADDR2_B  0x00000585
#define MSR_IA32_RTIT_ADDR3_B  0x00000587
 
typedef union {
  struct {
    UINT32    VirtualAddress   : 32;
    UINT32    VirtualAddressHi : 16;
    UINT32    SignExt_VA       : 16;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_RTIT_ADDR_REGISTER;
 
#define MSR_IA32_DS_AREA  0x00000600
 
#define MSR_IA32_TSC_DEADLINE  0x000006E0
 
#define MSR_IA32_PM_ENABLE  0x00000770
 
typedef union {
  struct {
    UINT32    HWP_ENABLE : 1;
    UINT32    Reserved1  : 31;
    UINT32    Reserved2  : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_PM_ENABLE_REGISTER;
 
#define MSR_IA32_HWP_CAPABILITIES  0x00000771
 
typedef union {
  struct {
    UINT32    Highest_Performance        : 8;
    UINT32    Guaranteed_Performance     : 8;
    UINT32    Most_Efficient_Performance : 8;
    UINT32    Lowest_Performance         : 8;
    UINT32    Reserved                   : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_HWP_CAPABILITIES_REGISTER;
 
#define MSR_IA32_HWP_REQUEST_PKG  0x00000772
 
typedef union {
  struct {
    UINT32    Minimum_Performance           : 8;
    UINT32    Maximum_Performance           : 8;
    UINT32    Desired_Performance           : 8;
    UINT32    Energy_Performance_Preference : 8;
    UINT32    Activity_Window               : 10;
    UINT32    Reserved                      : 22;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_HWP_REQUEST_PKG_REGISTER;
 
#define MSR_IA32_HWP_INTERRUPT  0x00000773
 
typedef union {
  struct {
    UINT32    EN_Guaranteed_Performance_Change : 1;
    UINT32    EN_Excursion_Minimum             : 1;
    UINT32    Reserved1                        : 30;
    UINT32    Reserved2                        : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_HWP_INTERRUPT_REGISTER;
 
#define MSR_IA32_HWP_REQUEST  0x00000774
 
typedef union {
  struct {
    UINT32    Minimum_Performance           : 8;
    UINT32    Maximum_Performance           : 8;
    UINT32    Desired_Performance           : 8;
    UINT32    Energy_Performance_Preference : 8;
    UINT32    Activity_Window               : 10;
    UINT32    Package_Control               : 1;
    UINT32    Reserved                      : 21;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_HWP_REQUEST_REGISTER;
 
#define MSR_IA32_HWP_STATUS  0x00000777
 
typedef union {
  struct {
    UINT32    Guaranteed_Performance_Change : 1;
    UINT32    Reserved1                     : 1;
    UINT32    Excursion_To_Minimum          : 1;
    UINT32    Reserved2                     : 29;
    UINT32    Reserved3                     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_HWP_STATUS_REGISTER;
 
#define MSR_IA32_X2APIC_APICID  0x00000802
 
#define MSR_IA32_X2APIC_VERSION  0x00000803
 
#define MSR_IA32_X2APIC_TPR  0x00000808
 
#define MSR_IA32_X2APIC_PPR  0x0000080A
 
#define MSR_IA32_X2APIC_EOI  0x0000080B
 
#define MSR_IA32_X2APIC_LDR  0x0000080D
 
#define MSR_IA32_X2APIC_SIVR  0x0000080F
 
#define MSR_IA32_X2APIC_ISR0  0x00000810
#define MSR_IA32_X2APIC_ISR1  0x00000811
#define MSR_IA32_X2APIC_ISR2  0x00000812
#define MSR_IA32_X2APIC_ISR3  0x00000813
#define MSR_IA32_X2APIC_ISR4  0x00000814
#define MSR_IA32_X2APIC_ISR5  0x00000815
#define MSR_IA32_X2APIC_ISR6  0x00000816
#define MSR_IA32_X2APIC_ISR7  0x00000817
 
#define MSR_IA32_X2APIC_TMR0  0x00000818
#define MSR_IA32_X2APIC_TMR1  0x00000819
#define MSR_IA32_X2APIC_TMR2  0x0000081A
#define MSR_IA32_X2APIC_TMR3  0x0000081B
#define MSR_IA32_X2APIC_TMR4  0x0000081C
#define MSR_IA32_X2APIC_TMR5  0x0000081D
#define MSR_IA32_X2APIC_TMR6  0x0000081E
#define MSR_IA32_X2APIC_TMR7  0x0000081F
 
#define MSR_IA32_X2APIC_IRR0  0x00000820
#define MSR_IA32_X2APIC_IRR1  0x00000821
#define MSR_IA32_X2APIC_IRR2  0x00000822
#define MSR_IA32_X2APIC_IRR3  0x00000823
#define MSR_IA32_X2APIC_IRR4  0x00000824
#define MSR_IA32_X2APIC_IRR5  0x00000825
#define MSR_IA32_X2APIC_IRR6  0x00000826
#define MSR_IA32_X2APIC_IRR7  0x00000827
 
#define MSR_IA32_X2APIC_ESR  0x00000828
 
#define MSR_IA32_X2APIC_LVT_CMCI  0x0000082F
 
#define MSR_IA32_X2APIC_ICR  0x00000830
 
#define MSR_IA32_X2APIC_LVT_TIMER  0x00000832
 
#define MSR_IA32_X2APIC_LVT_THERMAL  0x00000833
 
#define MSR_IA32_X2APIC_LVT_PMI  0x00000834
 
#define MSR_IA32_X2APIC_LVT_LINT0  0x00000835
 
#define MSR_IA32_X2APIC_LVT_LINT1  0x00000836
 
#define MSR_IA32_X2APIC_LVT_ERROR  0x00000837
 
#define MSR_IA32_X2APIC_INIT_COUNT  0x00000838
 
#define MSR_IA32_X2APIC_CUR_COUNT  0x00000839
 
#define MSR_IA32_X2APIC_DIV_CONF  0x0000083E
 
#define MSR_IA32_X2APIC_SELF_IPI  0x0000083F
 
#define MSR_IA32_DEBUG_INTERFACE  0x00000C80
 
typedef union {
  struct {
    UINT32    Enable        : 1;
    UINT32    Reserved1     : 29;
    UINT32    Lock          : 1;
    UINT32    DebugOccurred : 1;
    UINT32    Reserved2     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_DEBUG_INTERFACE_REGISTER;
 
#define MSR_IA32_L3_QOS_CFG  0x00000C81
 
typedef union {
  struct {
    UINT32    Enable    : 1;
    UINT32    Reserved1 : 31;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_L3_QOS_CFG_REGISTER;
 
#define MSR_IA32_L2_QOS_CFG  0x00000C82
 
typedef union {
  struct {
    UINT32    Enable    : 1;
    UINT32    Reserved1 : 31;
    UINT32    Reserved2 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_L2_QOS_CFG_REGISTER;
 
#define MSR_IA32_QM_EVTSEL  0x00000C8D
 
typedef union {
  struct {
    UINT32    EventID              : 8;
    UINT32    Reserved             : 24;
    UINT32    ResourceMonitoringID : 32;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_QM_EVTSEL_REGISTER;
 
#define MSR_IA32_QM_CTR  0x00000C8E
 
typedef union {
  struct {
    UINT32    ResourceMonitoredData   : 32;
    UINT32    ResourceMonitoredDataHi : 30;
    UINT32    Unavailable             : 1;
    UINT32    Error                   : 1;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_QM_CTR_REGISTER;
 
#define MSR_IA32_PQR_ASSOC  0x00000C8F
 
typedef union {
  struct {
    UINT32    ResourceMonitoringID : 32;
    UINT32    COS                  : 32;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_PQR_ASSOC_REGISTER;
 
#define MSR_IA32_BNDCFGS  0x00000D90
 
typedef union {
  struct {
    UINT32    EN          : 1;
    UINT32    BNDPRESERVE : 1;
    UINT32    Reserved    : 10;
    UINT32    Base        : 20;
    UINT32    BaseHi      : 32;
  } Bits;
  UINT64    Uint64;
} MSR_IA32_BNDCFGS_REGISTER;
 
#define MSR_IA32_XSS  0x00000DA0
 
typedef union {
  struct {
    UINT32    Reserved1                     : 8;
    UINT32    TracePacketConfigurationState : 1;
    UINT32    Reserved2                     : 23;
    UINT32    Reserved3                     : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_XSS_REGISTER;
 
#define MSR_IA32_PKG_HDC_CTL  0x00000DB0
 
typedef union {
  struct {
    UINT32    HDC_Pkg_Enable : 1;
    UINT32    Reserved1      : 31;
    UINT32    Reserved2      : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_PKG_HDC_CTL_REGISTER;
 
#define MSR_IA32_PM_CTL1  0x00000DB1
 
typedef union {
  struct {
    UINT32    HDC_Allow_Block : 1;
    UINT32    Reserved1       : 31;
    UINT32    Reserved2       : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_PM_CTL1_REGISTER;
 
#define MSR_IA32_THREAD_STALL  0x00000DB2
 
#define MSR_IA32_EFER  0xC0000080
 
typedef union {
  struct {
    UINT32    SCE       : 1;
    UINT32    Reserved1 : 7;
    UINT32    LME       : 1;
    UINT32    Reserved2 : 1;
    UINT32    LMA       : 1;
    UINT32    NXE       : 1;
    UINT32    Reserved3 : 20;
    UINT32    Reserved4 : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_EFER_REGISTER;
 
#define MSR_IA32_STAR  0xC0000081
 
#define MSR_IA32_LSTAR  0xC0000082
 
#define MSR_IA32_CSTAR  0xC0000083
 
#define MSR_IA32_FMASK  0xC0000084
 
#define MSR_IA32_FS_BASE  0xC0000100
 
#define MSR_IA32_GS_BASE  0xC0000101
 
#define MSR_IA32_KERNEL_GS_BASE  0xC0000102
 
#define MSR_IA32_TSC_AUX  0xC0000103
 
typedef union {
  struct {
    UINT32    AUX      : 32;
    UINT32    Reserved : 32;
  } Bits;
  UINT32    Uint32;
  UINT64    Uint64;
} MSR_IA32_TSC_AUX_REGISTER;
 
#endif