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Cpuid.h File Reference

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Data Structures

union  CPUID_VERSION_INFO_EAX
 
union  CPUID_VERSION_INFO_EBX
 
union  CPUID_VERSION_INFO_ECX
 
union  CPUID_VERSION_INFO_EDX
 
union  CPUID_CACHE_INFO_CACHE_TLB
 
union  CPUID_CACHE_PARAMS_EAX
 
union  CPUID_CACHE_PARAMS_EBX
 
union  CPUID_CACHE_PARAMS_EDX
 
union  CPUID_MONITOR_MWAIT_EAX
 
union  CPUID_MONITOR_MWAIT_EBX
 
union  CPUID_MONITOR_MWAIT_ECX
 
union  CPUID_MONITOR_MWAIT_EDX
 
union  CPUID_THERMAL_POWER_MANAGEMENT_EAX
 
union  CPUID_THERMAL_POWER_MANAGEMENT_EBX
 
union  CPUID_THERMAL_POWER_MANAGEMENT_ECX
 
union  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
 
union  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
 
union  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX
 
union  CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
 
union  CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
 
union  CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
 
union  CPUID_EXTENDED_TOPOLOGY_EAX
 
union  CPUID_EXTENDED_TOPOLOGY_EBX
 
union  CPUID_EXTENDED_TOPOLOGY_ECX
 
union  CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
 
union  CPUID_EXTENDED_STATE_SUB_LEAF_EAX
 
union  CPUID_EXTENDED_STATE_SUB_LEAF_ECX
 
union  CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
 
union  CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX
 
union  CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
 
union  CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
 
union  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX
 
union  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
 
union  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX
 
union  CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX
 
union  CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX
 
union  CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX
 
union  CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX
 
union  CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX
 
union  CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
 
union  CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX
 
union  CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX
 
union  CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX
 
union  CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX
 
union  CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX
 
union  CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
 
union  CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
 
union  CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
 
union  CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
 
union  CPUID_PROCESSOR_FREQUENCY_EAX
 
union  CPUID_PROCESSOR_FREQUENCY_EBX
 
union  CPUID_PROCESSOR_FREQUENCY_ECX
 
union  CPUID_SOC_VENDOR_MAIN_LEAF_EBX
 
union  CPUID_SOC_VENDOR_BRAND_STRING_DATA
 
union  CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX
 
union  CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX
 
union  CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX
 
union  CPUID_EXTENDED_CPU_SIG_ECX
 
union  CPUID_EXTENDED_CPU_SIG_EDX
 
union  CPUID_BRAND_STRING_DATA
 
union  CPUID_EXTENDED_CACHE_INFO_ECX
 
union  CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX
 
union  CPUID_VIR_PHY_ADDRESS_SIZE_EAX
 

Macros

#define CPUID_SIGNATURE   0x00
 
#define CPUID_VERSION_INFO   0x01
 
#define CPUID_CACHE_INFO   0x02
 
#define CPUID_SERIAL_NUMBER   0x03
 
#define CPUID_CACHE_PARAMS   0x04
 
#define CPUID_MONITOR_MWAIT   0x05
 
#define CPUID_THERMAL_POWER_MANAGEMENT   0x06
 
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS   0x07
 
#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO   0x00
 
#define CPUID_DIRECT_CACHE_ACCESS_INFO   0x09
 
#define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING   0x0A
 
#define CPUID_EXTENDED_TOPOLOGY   0x0B
 
#define CPUID_EXTENDED_STATE   0x0D
 
#define CPUID_EXTENDED_STATE_MAIN_LEAF   0x00
 
#define CPUID_EXTENDED_STATE_SUB_LEAF   0x01
 
#define CPUID_EXTENDED_STATE_SIZE_OFFSET   0x02
 
#define CPUID_INTEL_RDT_MONITORING   0x0F
 
#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF   0x00
 
#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF   0x01
 
#define CPUID_INTEL_RDT_ALLOCATION   0x10
 
#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF   0x00
 
#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF   0x01
 
#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF   0x02
 
#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF   0x03
 
#define CPUID_INTEL_SGX   0x12
 
#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF   0x00
 
#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF   0x01
 
#define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF   0x02
 
#define CPUID_INTEL_PROCESSOR_TRACE   0x14
 
#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF   0x00
 
#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF   0x01
 
#define CPUID_TIME_STAMP_COUNTER   0x15
 
#define CPUID_PROCESSOR_FREQUENCY   0x16
 
#define CPUID_SOC_VENDOR   0x17
 
#define CPUID_SOC_VENDOR_MAIN_LEAF   0x00
 
#define CPUID_SOC_VENDOR_BRAND_STRING1   0x01
 
#define CPUID_SOC_VENDOR_BRAND_STRING2   0x02
 
#define CPUID_SOC_VENDOR_BRAND_STRING3   0x03
 
#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS   0x18
 
#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF   0x00
 
#define CPUID_HYBRID_INFORMATION   0x1A
 
#define CPUID_HYBRID_INFORMATION_MAIN_LEAF   0x00
 
#define CPUID_V2_EXTENDED_TOPOLOGY   0x1F
 
#define CPUID_GUESTTD_RUNTIME_ENVIRONMENT   0x21
 
#define CPUID_EXTENDED_FUNCTION   0x80000000
 
#define CPUID_EXTENDED_CPU_SIG   0x80000001
 
#define CPUID_BRAND_STRING1   0x80000002
 
#define CPUID_BRAND_STRING2   0x80000003
 
#define CPUID_BRAND_STRING3   0x80000004
 
#define CPUID_EXTENDED_CACHE_INFO   0x80000006
 
#define CPUID_EXTENDED_TIME_STAMP_COUNTER   0x80000007
 
#define CPUID_VIR_PHY_ADDRESS_SIZE   0x80000008
 
#define CPUID_SIGNATURE_GENUINE_INTEL_EBX   SIGNATURE_32 ('G', 'e', 'n', 'u')
 
#define CPUID_SIGNATURE_GENUINE_INTEL_EDX   SIGNATURE_32 ('i', 'n', 'e', 'I')
 
#define CPUID_SIGNATURE_GENUINE_INTEL_ECX   SIGNATURE_32 ('n', 't', 'e', 'l')
 
#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR   0x00
 
#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR   0x01
 
#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR   0x02
 
#define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL   0x00
 
#define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA   0x01
 
#define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION   0x02
 
#define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED   0x03
 
#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID   0x00
 
#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT   0x01
 
#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE   0x02
 
#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID   0x00
 
#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB   0x01
 
#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB   0x02
 
#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB   0x03
 
#define CPUID_CORE_TYPE_INTEL_ATOM   0x20
 
#define CPUID_CORE_TYPE_INTEL_CORE   0x40
 
#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE   0x03
 
#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE   0x04
 
#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE   0x05
 
#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EBX   SIGNATURE_32 ('I', 'n', 't', 'e')
 
#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_ECX   SIGNATURE_32 (' ', ' ', ' ', ' ')
 
#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EDX   SIGNATURE_32 ('l', 'T', 'D', 'X')
 
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED   0x00
 
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED   0x01
 
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY   0x02
 
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY   0x04
 
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY   0x06
 
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY   0x08
 
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY   0x0A
 
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY   0x0B
 
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY   0x0C
 
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY   0x0D
 
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY   0x0E
 
#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL   0x0F
 

Detailed Description

Intel CPUID leaf definitions.

Provides defines for CPUID leaf indexes. Data structures are provided for registers returned by a CPUID leaf that contain one or more bit fields. If a register returned is a single 32-bit value, then a data structure is not provided for that register.

Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, November 2018, CPUID instruction. Architecture Specification: Intel(R) Trust Domain Extensions Module, Chap 10.2 344425-003US, August 2021

Definition in file Cpuid.h.

Macro Definition Documentation

◆ CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING

#define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING   0x0A

CPUID Architectural Performance Monitoring

Parameters
EAXCPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)
Return values
EAXArchitectural Performance Monitoring information described by the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.
EBXArchitectural Performance Monitoring information described by the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.
ECXReserved.
EDXArchitectural Performance Monitoring information described by the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.

Example usage

AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
#define NULL
Definition: Base.h:312
#define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING
Definition: Cpuid.h:1642
UINT32 EFIAPI AsmCpuid(IN UINT32 Index, OUT UINT32 *RegisterEax OPTIONAL, OUT UINT32 *RegisterEbx OPTIONAL, OUT UINT32 *RegisterEcx OPTIONAL, OUT UINT32 *RegisterEdx OPTIONAL)
Definition: CpuId.c:36

Definition at line 1642 of file Cpuid.h.

◆ CPUID_BRAND_STRING1

#define CPUID_BRAND_STRING1   0x80000002

CPUID Processor Brand String

Parameters
EAXCPUID_BRAND_STRING1 (0x80000002)
Return values
EAXProcessor Brand String in type CPUID_BRAND_STRING_DATA.
EBXProcessor Brand String Continued in type CPUID_BRAND_STRING_DATA.
ECXProcessor Brand String Continued in type CPUID_BRAND_STRING_DATA.
EDXProcessor Brand String Continued in type CPUID_BRAND_STRING_DATA.

Example usage

AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
#define CPUID_BRAND_STRING1
Definition: Cpuid.h:3857

Definition at line 3857 of file Cpuid.h.

◆ CPUID_BRAND_STRING2

#define CPUID_BRAND_STRING2   0x80000003

CPUID Processor Brand String

Parameters
EAXCPUID_BRAND_STRING2 (0x80000003)
Return values
EAXProcessor Brand String Continued in type CPUID_BRAND_STRING_DATA.
EBXProcessor Brand String Continued in type CPUID_BRAND_STRING_DATA.
ECXProcessor Brand String Continued in type CPUID_BRAND_STRING_DATA.
EDXProcessor Brand String Continued in type CPUID_BRAND_STRING_DATA.

Example usage

AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
#define CPUID_BRAND_STRING2
Definition: Cpuid.h:3894

Definition at line 3894 of file Cpuid.h.

◆ CPUID_BRAND_STRING3

#define CPUID_BRAND_STRING3   0x80000004

CPUID Processor Brand String

Parameters
EAXCPUID_BRAND_STRING3 (0x80000004)
Return values
EAXProcessor Brand String Continued in type CPUID_BRAND_STRING_DATA.
EBXProcessor Brand String Continued in type CPUID_BRAND_STRING_DATA.
ECXProcessor Brand String Continued in type CPUID_BRAND_STRING_DATA.
EDXProcessor Brand String Continued in type CPUID_BRAND_STRING_DATA.

Example usage

AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
#define CPUID_BRAND_STRING3
Definition: Cpuid.h:3916

Definition at line 3916 of file Cpuid.h.

◆ CPUID_CACHE_INFO

#define CPUID_CACHE_INFO   0x02

CPUID Cache and TLB Information

Parameters
EAXCPUID_CACHE_INFO (0x02)
Return values
EAXCache and TLB Information described by the type CPUID_CACHE_INFO_CACHE_TLB. CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns 0x01 and must be ignored. Only valid if CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
EBXCache and TLB Information described by the type CPUID_CACHE_INFO_CACHE_TLB. Only valid if CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
ECXCache and TLB Information described by the type CPUID_CACHE_INFO_CACHE_TLB. Only valid if CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
EDXCache and TLB Information described by the type CPUID_CACHE_INFO_CACHE_TLB. Only valid if CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.

Example usage

AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
#define CPUID_CACHE_INFO
Definition: Cpuid.h:710

Cache Descriptor values

Value Type Description
0x00 General Null descriptor, this byte contains no information
0x01 TLB Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries
0x02 TLB Instruction TLB: 4 MByte pages, fully associative, 2 entries
0x03 TLB Data TLB: 4 KByte pages, 4-way set associative, 64 entries
0x04 TLB Data TLB: 4 MByte pages, 4-way set associative, 8 entries
0x05 TLB Data TLB1: 4 MByte pages, 4-way set associative, 32 entries
0x06 Cache 1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size
0x08 Cache 1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size
0x09 Cache 1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size
0x0A Cache 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size
0x0B TLB Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries
0x0C Cache 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size
0x0D Cache 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size
0x0E Cache 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size
0x1D Cache 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size
0x21 Cache 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size
0x22 Cache 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector
0x23 Cache 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
0x24 Cache 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size
0x25 Cache 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
0x29 Cache 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
0x2C Cache 1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size
0x30 Cache 1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size
0x40 Cache No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache
0x41 Cache 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size
0x42 Cache 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size
0x43 Cache 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size
0x44 Cache 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size
0x45 Cache 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size
0x46 Cache 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size
0x47 Cache 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size
0x48 Cache 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size
0x49 Cache 3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H)
2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size
0x4A Cache 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size
0x4B Cache 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size
0x4C Cache 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size
0x4D Cache 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size
0x4E Cache 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size
0x4F TLB Instruction TLB: 4 KByte pages, 32 entries
0x50 TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries
0x51 TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries
0x52 TLB Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries
0x55 TLB Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries
0x56 TLB Data TLB0: 4 MByte pages, 4-way set associative, 16 entries
0x57 TLB Data TLB0: 4 KByte pages, 4-way associative, 16 entries
0x59 TLB Data TLB0: 4 KByte pages, fully associative, 16 entries
0x5A TLB Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries
0x5B TLB Data TLB: 4 KByte and 4 MByte pages, 64 entries
0x5C TLB Data TLB: 4 KByte and 4 MByte pages,128 entries
0x5D TLB Data TLB: 4 KByte and 4 MByte pages,256 entries
0x60 Cache 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size
0x61 TLB Instruction TLB: 4 KByte pages, fully associative, 48 entries
0x63 TLB Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries
0x64 TLB Data TLB: 4 KByte pages, 4-way set associative, 512 entries
0x66 Cache 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size
0x67 Cache 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size
0x68 Cache 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size
0x6A Cache uTLB: 4 KByte pages, 8-way set associative, 64 entries
0x6B Cache DTLB: 4 KByte pages, 8-way set associative, 256 entries
0x6C Cache DTLB: 2M/4M pages, 8-way set associative, 128 entries
0x6D Cache DTLB: 1 GByte pages, fully associative, 16 entries
0x70 Cache Trace cache: 12 K-uop, 8-way set associative
0x71 Cache Trace cache: 16 K-uop, 8-way set associative
0x72 Cache Trace cache: 32 K-uop, 8-way set associative
0x76 TLB Instruction TLB: 2M/4M pages, fully associative, 8 entries
0x78 Cache 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size
0x79 Cache 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
0x7A Cache 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
0x7B Cache 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
0x7C Cache 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector
0x7D Cache 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size
0x7F Cache 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size
0x80 Cache 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size
0x82 Cache 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size
0x83 Cache 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size
0x84 Cache 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size
0x85 Cache 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size
0x86 Cache 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size
0x87 Cache 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size
0xA0 DTLB DTLB: 4k pages, fully associative, 32 entries
0xB0 TLB Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries
0xB1 TLB Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
0xB2 TLB Instruction TLB: 4KByte pages, 4-way set associative, 64 entries
0xB3 TLB Data TLB: 4 KByte pages, 4-way set associative, 128 entries
0xB4 TLB Data TLB1: 4 KByte pages, 4-way associative, 256 entries
0xB5 TLB Instruction TLB: 4KByte pages, 8-way set associative, 64 entries
0xB6 TLB Instruction TLB: 4KByte pages, 8-way set associative, 128 entries
0xBA TLB Data TLB1: 4 KByte pages, 4-way associative, 64 entries
0xC0 TLB Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries
0xC1 STLB Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries
0xC2 DTLB DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries
0xC3 STLB Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.
0xC4 DTLB DTLB: 2M/4M Byte pages, 4-way associative, 32 entries
0xCA STLB Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries
0xD0 Cache 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size
0xD1 Cache 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size
0xD2 Cache 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size
0xD6 Cache 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size
0xD7 Cache 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size
0xD8 Cache 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size
0xDC Cache 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size
0xDD Cache 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size
0xDE Cache 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size
0xE2 Cache 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size
0xE3 Cache 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size
0xE4 Cache 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size
0xEA Cache 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size
0xEB Cache 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size
0xEC Cache 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size
0xF0 Prefetch64-Byte prefetching
0xF1 Prefetch128-Byte prefetching
0xFE General CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters.
0xFF General CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters

Definition at line 710 of file Cpuid.h.

◆ CPUID_CACHE_PARAMS

#define CPUID_CACHE_PARAMS   0x04

CPUID Cache Parameters

Parameters
EAXCPUID_CACHE_PARAMS (0x04)
ECXCache Level. Valid values start at 0. Software can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an index value of 0, until the parameters report the value associated with the CacheType field in CPUID_CACHE_PARAMS_EAX is 0.
Return values
EAXReturns cache type information described by the type CPUID_CACHE_PARAMS_EAX.
EBXReturns cache line and associativity information described by the type CPUID_CACHE_PARAMS_EBX.
ECXReturns the number of sets in the cache.
EDXReturns cache WINVD/INVD behavior described by the type CPUID_CACHE_PARAMS_EDX.

Example usage

UINT32 CacheLevel;
UINT32 Ecx;
CacheLevel = 0;
do {
CPUID_CACHE_PARAMS, CacheLevel,
&Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
);
CacheLevel++;
} while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
UINT32 EFIAPI AsmCpuidEx(IN UINT32 Index, IN UINT32 SubIndex, OUT UINT32 *RegisterEax OPTIONAL, OUT UINT32 *RegisterEbx OPTIONAL, OUT UINT32 *RegisterEcx OPTIONAL, OUT UINT32 *RegisterEdx OPTIONAL)
Definition: CpuIdEx.c:43
#define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL
Definition: Cpuid.h:866
#define CPUID_CACHE_PARAMS
Definition: Cpuid.h:802

Definition at line 802 of file Cpuid.h.

◆ CPUID_CACHE_PARAMS_CACHE_TYPE_DATA

#define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA   0x01

Definition at line 867 of file Cpuid.h.

◆ CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION

#define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION   0x02

Definition at line 868 of file Cpuid.h.

◆ CPUID_CACHE_PARAMS_CACHE_TYPE_NULL

#define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL   0x00

Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType

Definition at line 866 of file Cpuid.h.

◆ CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED

#define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED   0x03

Definition at line 869 of file Cpuid.h.

◆ CPUID_CORE_TYPE_INTEL_ATOM

#define CPUID_CORE_TYPE_INTEL_ATOM   0x20

Define value for CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX.CoreType

Definition at line 3650 of file Cpuid.h.

◆ CPUID_CORE_TYPE_INTEL_CORE

#define CPUID_CORE_TYPE_INTEL_CORE   0x40

Definition at line 3651 of file Cpuid.h.

◆ CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS

#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS   0x18

CPUID Deterministic Address Translation Parameters

Note
Each sub-leaf enumerates a different address translation structure. If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A sub-leaf index is also invalid if EDX[4:0] returns 0. Valid sub-leaves do not need to be contiguous or in any particular order. A valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or than a valid sub-leaf of a higher or lower-level structure. Some unified TLBs will allow a single TLB entry to satisfy data read/write and instruction fetches. Others will require separate entries (e.g., one loaded on data read/write and another loaded on an instruction fetch). Please see the Intel 64 and IA-32 Architectures Optimization Reference Manual for details of a particular product. Add one to the return value to get the result.
Parameters
EAXCPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)
ECXCPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00) CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*)

Definition at line 3457 of file Cpuid.h.

◆ CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF

#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF   0x00

CPUID Deterministic Address Translation Parameters

Parameters
EAXCPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)
ECXCPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)
Return values
EAXReports the maximum input value of supported sub-leaf in leaf 18H.
EBXReturns Deterministic Address Translation Parameters described by the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX.
ECXNumber of Sets.
EDXReturns Deterministic Address Translation Parameters described by the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.

Example usage

Definition at line 3486 of file Cpuid.h.

◆ CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB

#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB   0x01

Definition at line 3580 of file Cpuid.h.

◆ CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB

#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB   0x02

Definition at line 3581 of file Cpuid.h.

◆ CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID

#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID   0x00

◆ CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB

#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB   0x03

Definition at line 3582 of file Cpuid.h.

◆ CPUID_DIRECT_CACHE_ACCESS_INFO

#define CPUID_DIRECT_CACHE_ACCESS_INFO   0x09

CPUID Direct Cache Access Information

Parameters
EAXCPUID_DIRECT_CACHE_ACCESS_INFO (0x09)
Return values
EAXValue of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
EBXReserved.
ECXReserved.
EDXReserved.

Example usage

UINT32 Eax;
#define CPUID_DIRECT_CACHE_ACCESS_INFO
Definition: Cpuid.h:1618

Definition at line 1618 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO

#define CPUID_EXTENDED_CACHE_INFO   0x80000006

CPUID Extended Cache information

Parameters
EAXCPUID_EXTENDED_CACHE_INFO (0x80000006)
Return values
EAXReserved.
EBXReserved.
ECXExtended cache information described by the type CPUID_EXTENDED_CACHE_INFO_ECX.
EDXReserved.

Example usage

Definition at line 3936 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY

#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY   0x0E

Definition at line 3981 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY

#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY   0x08

Definition at line 3976 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY

#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY   0x02

Definition at line 3973 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY

#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY   0x0A

Definition at line 3977 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY

#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY   0x0B

Definition at line 3978 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY

#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY   0x04

Definition at line 3974 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY

#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY   0x0C

Definition at line 3979 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY

#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY   0x06

Definition at line 3975 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY

#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY   0x0D

Definition at line 3980 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED

#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED   0x01

Definition at line 3972 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED

#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED   0x00

Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity

Definition at line 3971 of file Cpuid.h.

◆ CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL

#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL   0x0F

Definition at line 3982 of file Cpuid.h.

◆ CPUID_EXTENDED_CPU_SIG

#define CPUID_EXTENDED_CPU_SIG   0x80000001

CPUID Extended Processor Signature and Feature Bits

Parameters
EAXCPUID_EXTENDED_CPU_SIG (0x80000001)
Return values
EAXCPUID_EXTENDED_CPU_SIG.
EBXReserved.
ECXExtended Processor Signature and Feature Bits information described by the type CPUID_EXTENDED_CPU_SIG_ECX.
EDXExtended Processor Signature and Feature Bits information described by the type CPUID_EXTENDED_CPU_SIG_EDX.

Example usage

UINT32 Eax;
AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
#define CPUID_EXTENDED_CPU_SIG
Definition: Cpuid.h:3763

Definition at line 3763 of file Cpuid.h.

◆ CPUID_EXTENDED_FUNCTION

#define CPUID_EXTENDED_FUNCTION   0x80000000

CPUID Extended Function

Parameters
EAXCPUID_EXTENDED_FUNCTION (0x80000000)
Return values
EAXMaximum Input Value for Extended Function CPUID Information.
EBXReserved.
ECXReserved.
EDXReserved.

Example usage

UINT32 Eax;
#define CPUID_EXTENDED_FUNCTION
Definition: Cpuid.h:3740

Definition at line 3740 of file Cpuid.h.

◆ CPUID_EXTENDED_STATE

#define CPUID_EXTENDED_STATE   0x0D

CPUID Extended State Information

Parameters
EAXCPUID_EXTENDED_STATE (0x0D)
ECXCPUID_EXTENDED_STATE_MAIN_LEAF (0x00). CPUID_EXTENDED_STATE_SUB_LEAF (0x01). CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.

Definition at line 1913 of file Cpuid.h.

◆ CPUID_EXTENDED_STATE_MAIN_LEAF

#define CPUID_EXTENDED_STATE_MAIN_LEAF   0x00

CPUID Extended State Information Main Leaf

Parameters
EAXCPUID_EXTENDED_STATE (0x0D)
ECXCPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
Return values
EAXReports the supported bits of the lower 32 bits of XCR0. XCR0[n] can be set to 1 only if EAX[n] is 1. The format of the extended state main leaf is described by the type CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.
EBXMaximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save area are not enabled.
ECXMaximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the XSAVE/XRSTOR save area required by all supported features in the processor, i.e., all the valid bit fields in XCR0.
EDXReports the supported bits of the upper 32 bits of XCR0. XCR0[n+32] can be set to 1 only if EDX[n] is 1.

Example usage

UINT32 Ebx;
UINT32 Ecx;
UINT32 Edx;
&Eax.Uint32, &Ebx, &Ecx, &Edx
);
#define CPUID_EXTENDED_STATE
Definition: Cpuid.h:1913
#define CPUID_EXTENDED_STATE_MAIN_LEAF
Definition: Cpuid.h:1948

Definition at line 1948 of file Cpuid.h.

◆ CPUID_EXTENDED_STATE_SIZE_OFFSET

#define CPUID_EXTENDED_STATE_SIZE_OFFSET   0x02

CPUID Extended State Information Size and Offset Sub Leaf

Note
Leaf 0DH output depends on the initial value in ECX. Each sub-leaf index (starting at position 2) is supported if it corresponds to a supported bit in either the XCR0 register or the IA32_XSS MSR. If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
Parameters
EAXCPUID_EXTENDED_STATE (0x0D)
ECXCPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
Return values
EAXThe size in bytes (from the offset specified in EBX) of the save area for an extended state feature associated with a valid sub-leaf index, n.
EBXThe offset in bytes of this extended state component's save area from the beginning of the XSAVE/XRSTOR area. This field reports 0 if the sub-leaf index, n, does not map to a valid bit in the XCR0 register.
ECXThe format of the extended state components's save area as described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX. This field reports 0 if the sub-leaf index, n, is invalid.
EDXThis field reports 0 if the sub-leaf index, n, is invalid; otherwise it is reserved.

Example usage

UINT32 Eax;
UINT32 Ebx;
UINT32 Edx;
UINTN SubLeaf;
for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
&Eax, &Ebx, &Ecx.Uint32, &Edx
);
}
UINT64 UINTN
#define CPUID_EXTENDED_STATE_SIZE_OFFSET
Definition: Cpuid.h:2142

Definition at line 2142 of file Cpuid.h.

◆ CPUID_EXTENDED_STATE_SUB_LEAF

#define CPUID_EXTENDED_STATE_SUB_LEAF   0x01

CPUID Extended State Information Sub Leaf

Parameters
EAXCPUID_EXTENDED_STATE (0x0D)
ECXCPUID_EXTENDED_STATE_SUB_LEAF (0x01)
Return values
EAXThe format of the extended state sub-leaf is described by the type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.
EBXThe size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.
ECXThe format of the extended state sub-leaf is described by the type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.
EDXReports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.

Example usage

Definition at line 2028 of file Cpuid.h.

◆ CPUID_EXTENDED_TIME_STAMP_COUNTER

#define CPUID_EXTENDED_TIME_STAMP_COUNTER   0x80000007

CPUID Extended Time Stamp Counter information

Parameters
EAXCPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)
Return values
EAXReserved.
EBXReserved.
ECXReserved.
EDXExtended time stamp counter (TSC) information described by the type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.

Example usage

Definition at line 4005 of file Cpuid.h.

◆ CPUID_EXTENDED_TOPOLOGY

#define CPUID_EXTENDED_TOPOLOGY   0x0B

CPUID Extended Topology Information

Note
CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking for the existence of Leaf 1FH before using leaf 0BH. Most of Leaf 0BH output depends on the initial value in ECX. The EDX output of leaf 0BH is always valid and does not vary with input value in ECX. Output value in ECX[7:0] always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index enumerates a higher-level topological entity in hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8].
Parameters
EAXCPUID_EXTENDED_TOPOLOGY (0x0B)
ECXLevel number
Return values
EAXExtended topology information described by the type CPUID_EXTENDED_TOPOLOGY_EAX.
EBXExtended topology information described by the type CPUID_EXTENDED_TOPOLOGY_EBX.
ECXExtended topology information described by the type CPUID_EXTENDED_TOPOLOGY_ECX.
EDXx2APIC ID the current logical processor.

Example usage

UINT32 Edx;
UINT32 LevelNumber;
LevelNumber = 0;
do {
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
);
LevelNumber++;
} while (Eax.Bits.ApicIdShift != 0);
#define CPUID_EXTENDED_TOPOLOGY
Definition: Cpuid.h:1810

Definition at line 1810 of file Cpuid.h.

◆ CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE

#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE   0x02

Definition at line 1899 of file Cpuid.h.

◆ CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID

#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID   0x00

Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType

Definition at line 1897 of file Cpuid.h.

◆ CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT

#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT   0x01

Definition at line 1898 of file Cpuid.h.

◆ CPUID_GUESTTD_RUNTIME_ENVIRONMENT

#define CPUID_GUESTTD_RUNTIME_ENVIRONMENT   0x21

CPUID Guest TD Run Time Environment Enumeration Leaf

Note
Guest software can be designed to run either as a TD, as a legacy virtual machine, or directly on the CPU, based on enumeration of its run-time environment. CPUID leaf 21H emulation is done by the Intel TDX module. Sub-leaf 0 returns the values shown below. Other sub-leaves return 0 in EAX/EBX/ECX/EDX. EAX: 0x00000000 EBX: 0x65746E49 "Inte" ECX: 0x20202020 " " EDX: 0x5844546C "lTDX"
Parameters
EAXCPUID_GUESTTD_RUNTIME_ENVIRONMENT (0x21)
ECXLevel number

Definition at line 3711 of file Cpuid.h.

◆ CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EBX

#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EBX   SIGNATURE_32 ('I', 'n', 't', 'e')

CPUID Guest TD signature values returned by Intel processors

Definition at line 3716 of file Cpuid.h.

◆ CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_ECX

#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_ECX   SIGNATURE_32 (' ', ' ', ' ', ' ')

Definition at line 3717 of file Cpuid.h.

◆ CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EDX

#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EDX   SIGNATURE_32 ('l', 'T', 'D', 'X')

Definition at line 3718 of file Cpuid.h.

◆ CPUID_HYBRID_INFORMATION

#define CPUID_HYBRID_INFORMATION   0x1A

CPUID Hybrid Information Enumeration Leaf

Parameters
EAXCPUID_HYBRID_INFORMATION (0x1A)
ECXCPUID_HYBRID_INFORMATION_MAIN_LEAF (0x00).
Return values
EAXEnumerates the native model ID and core type described by the type CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX
EBXReserved.
ECXReserved.
EDXReserved.

Example usage

Definition at line 3611 of file Cpuid.h.

◆ CPUID_HYBRID_INFORMATION_MAIN_LEAF

#define CPUID_HYBRID_INFORMATION_MAIN_LEAF   0x00

CPUID Hybrid Information Enumeration main leaf

Definition at line 3616 of file Cpuid.h.

◆ CPUID_INTEL_PROCESSOR_TRACE

#define CPUID_INTEL_PROCESSOR_TRACE   0x14

CPUID Intel Processor Trace Information

Parameters
EAXCPUID_INTEL_PROCESSOR_TRACE (0x14)
ECXCPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00). CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).

Definition at line 2919 of file Cpuid.h.

◆ CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF

#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF   0x00

CPUID Intel Processor Trace Information Main Leaf

Parameters
EAXCPUID_INTEL_PROCEDSSOR_TRACE (0x14)
ECXCPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)
Return values
EAXReports the maximum sub-leaf supported in leaf 14H.
EBXReturns Intel processor trace information described by the type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.
ECXReturns Intel processor trace information described by the type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.
EDXReserved.

Example usage

Definition at line 2946 of file Cpuid.h.

◆ CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF

#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF   0x01

CPUID Intel Processor Trace Information Sub-leaf

Parameters
EAXCPUID_INTEL_PROCEDSSOR_TRACE (0x14)
ECXCPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)
Return values
EAXReturns Intel processor trace information described by the type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.
EBXReturns Intel processor trace information described by the type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.
ECXReserved.
EDXReserved.

Example usage

UINT32 MaximumSubLeaf;
UINT32 SubLeaf;
&MaximumSubLeaf, NULL, NULL, NULL
);
for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
&Eax.Uint32, &Ebx.Uint32, NULL, NULL
);
}
#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF
Definition: Cpuid.h:3072

Definition at line 3072 of file Cpuid.h.

◆ CPUID_INTEL_RDT_ALLOCATION

#define CPUID_INTEL_RDT_ALLOCATION   0x10

CPUID Intel Resource Director Technology (Intel RDT) Allocation Information

Parameters
EAXCPUID_INTEL_RDT_ALLOCATION (0x10).
ECXCPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00). CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01). CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).

Definition at line 2298 of file Cpuid.h.

◆ CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF

#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF   0x00

Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf

Parameters
EAXCPUID_INTEL_RDT_ALLOCATION (0x10)
ECXCPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
Return values
EAXReserved.
EBXL3 and L2 Cache Allocation Technology information described by the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.
ECXReserved.
EDXReserved.

Example usage

Definition at line 2322 of file Cpuid.h.

◆ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF

#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF   0x02

L2 Cache Allocation Technology Enumeration Sub-leaf

Parameters
EAXCPUID_INTEL_RDT_ALLOCATION (0x10)
ECXCPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)
Return values
EAXRESID L2 Cache Allocation Technology information described by the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.
EBXBit-granular map of isolation/contention of allocation units.
ECXReserved.
EDXRESID L2 Cache Allocation Technology information described by the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.

Example usage

Definition at line 2477 of file Cpuid.h.

◆ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF

#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF   0x01

L3 Cache Allocation Technology Enumeration Sub-leaf

Parameters
EAXCPUID_INTEL_RDT_ALLOCATION (0x10)
ECXCPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)
Return values
EAXRESID L3 Cache Allocation Technology information described by the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.
EBXBit-granular map of isolation/contention of allocation units.
ECXRESID L3 Cache Allocation Technology information described by the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.
EDXRESID L3 Cache Allocation Technology information described by the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.

Example usage

Definition at line 2382 of file Cpuid.h.

◆ CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF

#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF   0x03

Memory Bandwidth Allocation Enumeration Sub-leaf

Parameters
EAXCPUID_INTEL_RDT_ALLOCATION (0x10)
ECXCPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03)
Return values
EAXRESID memory bandwidth Allocation Technology information described by the type CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX.
EBXReserved.
ECXRESID memory bandwidth Allocation Technology information described by the type CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX.
EDXRESID memory bandwidth Allocation Technology information described by the type CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX.

Example usage

Definition at line 2555 of file Cpuid.h.

◆ CPUID_INTEL_RDT_MONITORING

#define CPUID_INTEL_RDT_MONITORING   0x0F

CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information

Parameters
EAXCPUID_INTEL_RDT_MONITORING (0x0F)
ECXCPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00). CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).

Definition at line 2182 of file Cpuid.h.

◆ CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF

#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF   0x00

CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information Enumeration Sub-leaf

Parameters
EAXCPUID_INTEL_RDT_MONITORING (0x0F)
ECXCPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)
Return values
EAXReserved.
EBXMaximum range (zero-based) of RMID within this physical processor of all types.
ECXReserved.
EDXL3 Cache Intel RDT Monitoring Information Enumeration described by the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.

Example usage

Definition at line 2209 of file Cpuid.h.

◆ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF

#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF   0x01

CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf

Parameters
EAXCPUID_INTEL_RDT_MONITORING (0x0F)
ECXCPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)
Return values
EAXReserved.
EBXConversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
ECXMaximum range (zero-based) of RMID of this resource type.
EDXL3 Cache Intel RDT Monitoring Capability information described by the type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.

Example usage

Definition at line 2258 of file Cpuid.h.

◆ CPUID_INTEL_SGX

#define CPUID_INTEL_SGX   0x12

Intel SGX resource capability and configuration. See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".

If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying CPUID with EAX=12H on Intel SGX resource capability and configuration.

Parameters
EAXCPUID_INTEL_SGX (0x12)
ECXCPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00). CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01). CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02). Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0]) until the sub-leaf type is invalid.

Definition at line 2643 of file Cpuid.h.

◆ CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF

#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF   0x00

Sub-Leaf 0 Enumeration of Intel SGX Capabilities. Enumerates Intel SGX capability, including enclave instruction opcode support.

Parameters
EAXCPUID_INTEL_SGX (0x12)
ECXCPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)
Return values
EAXThe format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.
EBXMISCSELECT: Reports the bit vector of supported extended features that can be written to the MISC region of the SSA.
ECXReserved.
EDXThe format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.

Example usage

Definition at line 2672 of file Cpuid.h.

◆ CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF

#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF   0x01

Sub-Leaf 1 Enumeration of Intel SGX Capabilities. Enumerates Intel SGX capability of processor state configuration and enclave configuration in the SECS structure.

Parameters
EAXCPUID_INTEL_SGX (0x12)
ECXCPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)
Return values
EAXReport the valid bits of SECS.ATTRIBUTES[31:0] that software can set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE only if EAX[n] is 1, where n < 32.
EBXReport the valid bits of SECS.ATTRIBUTES[63:32] that software can set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE only if EBX[n] is 1, where n < 32.
ECXReport the valid bits of SECS.ATTRIBUTES[95:64] that software can set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE only if ECX[n] is 1, where n < 32.
EDXReport the valid bits of SECS.ATTRIBUTES[127:96] that software can set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE only if EDX[n] is 1, where n < 32.

Example usage

UINT32 Eax;
UINT32 Ebx;
UINT32 Ecx;
UINT32 Edx;
&Eax, &Ebx, &Ecx, &Edx
);
#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF
Definition: Cpuid.h:2771

Definition at line 2771 of file Cpuid.h.

◆ CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF

#define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF   0x02

Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources. Enumerates available EPC resources.

Parameters
EAXCPUID_INTEL_SGX (0x12)
ECXCPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)
Return values
EAXThe format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources is described by the type CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.
EBXThe format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources is described by the type CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.
EDXThe format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources is described by the type CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.
EDXThe format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources is described by the type CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.

Example usage

Definition at line 2806 of file Cpuid.h.

◆ CPUID_MONITOR_MWAIT

#define CPUID_MONITOR_MWAIT   0x05

CPUID MONITOR/MWAIT Information

Parameters
EAXCPUID_MONITOR_MWAIT (0x05)
Return values
EAXSmallest monitor-line size in bytes described by the type CPUID_MONITOR_MWAIT_EAX.
EBXLargest monitor-line size in bytes described by the type CPUID_MONITOR_MWAIT_EBX.
ECXEnumeration of Monitor-Mwait extensions support described by the type CPUID_MONITOR_MWAIT_ECX.
EDXSub C-states supported described by the type CPUID_MONITOR_MWAIT_EDX.

Example usage

Definition at line 967 of file Cpuid.h.

◆ CPUID_PROCESSOR_FREQUENCY

#define CPUID_PROCESSOR_FREQUENCY   0x16

CPUID Processor Frequency Information

Note
Data is returned from this interface in accordance with the processor's specification and does not reflect actual values. Suitable use of this data includes the display of processor information in like manner to the processor brand string and for determining the appropriate range to use when displaying processor information e.g. frequency history graphs. The returned information should not be used for any other purpose as the returned information does not accurately correlate to information / counters returned by other processor interfaces. While a processor may support the Processor Frequency Information leaf, fields that return a value of zero are not supported.
Parameters
EAXCPUID_TIME_STAMP_COUNTER (0x16)
Return values
EAXReturns processor base frequency information described by the type CPUID_PROCESSOR_FREQUENCY_EAX.
EBXReturns maximum frequency information described by the type CPUID_PROCESSOR_FREQUENCY_EBX.
ECXReturns bus frequency information described by the type CPUID_PROCESSOR_FREQUENCY_ECX.
EDXReserved.

Example usage

Definition at line 3189 of file Cpuid.h.

◆ CPUID_SERIAL_NUMBER

#define CPUID_SERIAL_NUMBER   0x03

CPUID Processor Serial Number

Processor serial number (PSN) is not supported in the Pentium 4 processor or later. On all models, use the PSN flag (returned using CPUID) to check for PSN support before accessing the feature.

Parameters
EAXCPUID_SERIAL_NUMBER (0x03)
Return values
EAXReserved.
EBXReserved.
ECXBits 31:0 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the value in this register is reserved.)
EDXBits 63:32 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the value in this register is reserved.)

Example usage

UINT32 Ecx;
UINT32 Edx;
#define CPUID_SERIAL_NUMBER
Definition: Cpuid.h:764

Definition at line 764 of file Cpuid.h.

◆ CPUID_SIGNATURE

#define CPUID_SIGNATURE   0x00

CPUID Signature Information

Parameters
EAXCPUID_SIGNATURE (0x00)
Return values
EAXReturns the highest value the CPUID instruction recognizes for returning basic processor information. The value is returned is processor specific.
EBXFirst 4 characters of a vendor identification string.
ECXLast 4 characters of a vendor identification string.
EDXMiddle 4 characters of a vendor identification string.

Example usage

UINT32 Eax;
UINT32 Ebx;
UINT32 Ecx;
UINT32 Edx;
AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
#define CPUID_SIGNATURE
Definition: Cpuid.h:45

Definition at line 45 of file Cpuid.h.

◆ CPUID_SIGNATURE_GENUINE_INTEL_EBX

#define CPUID_SIGNATURE_GENUINE_INTEL_EBX   SIGNATURE_32 ('G', 'e', 'n', 'u')

CPUID signature values returned by Intel processors

Definition at line 50 of file Cpuid.h.

◆ CPUID_SIGNATURE_GENUINE_INTEL_ECX

#define CPUID_SIGNATURE_GENUINE_INTEL_ECX   SIGNATURE_32 ('n', 't', 'e', 'l')

Definition at line 52 of file Cpuid.h.

◆ CPUID_SIGNATURE_GENUINE_INTEL_EDX

#define CPUID_SIGNATURE_GENUINE_INTEL_EDX   SIGNATURE_32 ('i', 'n', 'e', 'I')

Definition at line 51 of file Cpuid.h.

◆ CPUID_SOC_VENDOR

#define CPUID_SOC_VENDOR   0x17

CPUID SoC Vendor Information

Parameters
EAXCPUID_SOC_VENDOR (0x17)
ECXCPUID_SOC_VENDOR_MAIN_LEAF (0x00) CPUID_SOC_VENDOR_BRAND_STRING1 (0x01) CPUID_SOC_VENDOR_BRAND_STRING1 (0x02) CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)
Note
Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC Vendor Brand String is constructed by concatenating in ascending order of EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.

Definition at line 3270 of file Cpuid.h.

◆ CPUID_SOC_VENDOR_BRAND_STRING1

#define CPUID_SOC_VENDOR_BRAND_STRING1   0x01

CPUID SoC Vendor Information

Parameters
EAXCPUID_SOC_VENDOR (0x17)
ECXCPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
Return values
EAXSOC Vendor Brand String. UTF-8 encoded string of type CPUID_SOC_VENDOR_BRAND_STRING_DATA.
EBXSOC Vendor Brand String. UTF-8 encoded string of type CPUID_SOC_VENDOR_BRAND_STRING_DATA.
ECXSOC Vendor Brand String. UTF-8 encoded string of type CPUID_SOC_VENDOR_BRAND_STRING_DATA.
EDXSOC Vendor Brand String. UTF-8 encoded string of type CPUID_SOC_VENDOR_BRAND_STRING_DATA.

Example usage

Definition at line 3357 of file Cpuid.h.

◆ CPUID_SOC_VENDOR_BRAND_STRING2

#define CPUID_SOC_VENDOR_BRAND_STRING2   0x02

CPUID SoC Vendor Information

Parameters
EAXCPUID_SOC_VENDOR (0x17)
ECXCPUID_SOC_VENDOR_BRAND_STRING2 (0x02)
Return values
EAXSOC Vendor Brand String. UTF-8 encoded string of type CPUID_SOC_VENDOR_BRAND_STRING_DATA.
EBXSOC Vendor Brand String. UTF-8 encoded string of type CPUID_SOC_VENDOR_BRAND_STRING_DATA.
ECXSOC Vendor Brand String. UTF-8 encoded string of type CPUID_SOC_VENDOR_BRAND_STRING_DATA.
EDXSOC Vendor Brand String. UTF-8 encoded string of type CPUID_SOC_VENDOR_BRAND_STRING_DATA.

Example usage

Definition at line 3402 of file Cpuid.h.

◆ CPUID_SOC_VENDOR_BRAND_STRING3

#define CPUID_SOC_VENDOR_BRAND_STRING3   0x03

CPUID SoC Vendor Information

Parameters
EAXCPUID_SOC_VENDOR (0x17)
ECXCPUID_SOC_VENDOR_BRAND_STRING3 (0x03)
Return values
EAXSOC Vendor Brand String. UTF-8 encoded string of type CPUID_SOC_VENDOR_BRAND_STRING_DATA.
EBXSOC Vendor Brand String. UTF-8 encoded string of type CPUID_SOC_VENDOR_BRAND_STRING_DATA.
ECXSOC Vendor Brand String. UTF-8 encoded string of type CPUID_SOC_VENDOR_BRAND_STRING_DATA.
EDXSOC Vendor Brand String. UTF-8 encoded string of type CPUID_SOC_VENDOR_BRAND_STRING_DATA.

Example usage

Definition at line 3432 of file Cpuid.h.

◆ CPUID_SOC_VENDOR_MAIN_LEAF

#define CPUID_SOC_VENDOR_MAIN_LEAF   0x00

CPUID SoC Vendor Information

Parameters
EAXCPUID_SOC_VENDOR (0x17)
ECXCPUID_SOC_VENDOR_MAIN_LEAF (0x00)
Return values
EAXMaxSOCID_Index. Reports the maximum input value of supported sub-leaf in leaf 17H.
EBXReturns SoC Vendor information described by the type CPUID_SOC_VENDOR_MAIN_LEAF_EBX.
ECXProject ID. A unique number an SOC vendor assigns to its SOC projects.
EDXStepping ID. A unique number within an SOC project that an SOC vendor assigns.

Example usage

UINT32 Eax;
UINT32 Ecx;
UINT32 Edx;
&Eax, &Ebx.Uint32, &Ecx, &Edx
);
#define CPUID_SOC_VENDOR_MAIN_LEAF
Definition: Cpuid.h:3300

Definition at line 3300 of file Cpuid.h.

◆ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS

#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS   0x07

CPUID Structured Extended Feature Flags Enumeration

Parameters
EAXCPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
ECXCPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).
Note
If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.
Return values
EAXThe maximum input value for ECX to retrieve sub-leaf information.
EBXStructured Extended Feature Flags described by the type CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
ECXStructured Extended Feature Flags described by the type CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
EDXReserved.

Example usage

Definition at line 1301 of file Cpuid.h.

◆ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO

#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO   0x00

CPUID Structured Extended Feature Flags Enumeration sub-leaf

Definition at line 1306 of file Cpuid.h.

◆ CPUID_THERMAL_POWER_MANAGEMENT

#define CPUID_THERMAL_POWER_MANAGEMENT   0x06

CPUID Thermal and Power Management

Parameters
EAXCPUID_THERMAL_POWER_MANAGEMENT (0x06)
Return values
EAXThermal and power management features described by the type CPUID_THERMAL_POWER_MANAGEMENT_EAX.
EBXNumber of Interrupt Thresholds in Digital Thermal Sensor described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.
ECXPerformance features described by the type CPUID_THERMAL_POWER_MANAGEMENT_ECX.
EDXReserved.

Example usage

Definition at line 1114 of file Cpuid.h.

◆ CPUID_TIME_STAMP_COUNTER

#define CPUID_TIME_STAMP_COUNTER   0x15

CPUID Time Stamp Counter and Nominal Core Crystal Clock Information

Note
If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated. EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency. If ECX is 0, the nominal core crystal clock frequency is not enumerated. "TSC frequency" = "core crystal clock frequency" * EBX/EAX. The core crystal clock may differ from the reference clock, bus clock, or core clock frequencies.
Parameters
EAXCPUID_TIME_STAMP_COUNTER (0x15)
Return values
EAXAn unsigned integer which is the denominator of the TSC/"core crystal clock" ratio
EBXAn unsigned integer which is the numerator of the TSC/"core crystal clock" ratio.
ECXAn unsigned integer which is the nominal frequency of the core crystal clock in Hz.
EDXReserved.

Example usage

UINT32 Eax;
UINT32 Ebx;
UINT32 Ecx;
AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
#define CPUID_TIME_STAMP_COUNTER
Definition: Cpuid.h:3154

Definition at line 3154 of file Cpuid.h.

◆ CPUID_V2_EXTENDED_TOPOLOGY

#define CPUID_V2_EXTENDED_TOPOLOGY   0x1F

CPUID V2 Extended Topology Enumeration Leaf

Note
CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking for the existence of Leaf 1FH and using this if available. Most of Leaf 1FH output depends on the initial value in ECX. The EDX output of leaf 1FH is always valid and does not vary with input value in ECX. Output value in ECX[7:0] always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index enumerates a higher-level topological entity in hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8].

Software should use this field (EAX[4:0]) to enumerate processor topology of the system. Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical processors available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software and platform hardware configurations.

Parameters
EAXCPUID_V2_EXTENDED_TOPOLOGY (0x1F)
ECXLevel number

Definition at line 3680 of file Cpuid.h.

◆ CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE

#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE   0x05

Definition at line 3689 of file Cpuid.h.

◆ CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE

#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE   0x03

Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType The value of the "level type" field is not related to level numbers in any way, higher "level type" values do not mean higher levels.

Definition at line 3687 of file Cpuid.h.

◆ CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE

#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE   0x04

Definition at line 3688 of file Cpuid.h.

◆ CPUID_VERSION_INFO

#define CPUID_VERSION_INFO   0x01

CPUID Version Information

Parameters
EAXCPUID_VERSION_INFO (0x01)
Return values
EAXReturns Model, Family, Stepping Information described by the type CPUID_VERSION_INFO_EAX.
EBXReturns Brand, Cache Line Size, and Initial APIC ID described by the type CPUID_VERSION_INFO_EBX.
ECXCPU Feature Information described by the type CPUID_VERSION_INFO_ECX.
EDXCPU Feature Information described by the type CPUID_VERSION_INFO_EDX.

Example usage

Definition at line 81 of file Cpuid.h.

◆ CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR

#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR   0x02

Definition at line 112 of file Cpuid.h.

◆ CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR

#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR   0x01

Definition at line 111 of file Cpuid.h.

◆ CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR

#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR   0x00

Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType

Definition at line 110 of file Cpuid.h.

◆ CPUID_VIR_PHY_ADDRESS_SIZE

#define CPUID_VIR_PHY_ADDRESS_SIZE   0x80000008

CPUID Linear Physical Address Size

Parameters
EAXCPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
Return values
EAXLinear/Physical Address Size described by the type CPUID_VIR_PHY_ADDRESS_SIZE_EAX.
EBXReserved.
ECXReserved.
EDXReserved.

Example usage

Definition at line 4047 of file Cpuid.h.