TianoCore EDK2 master
Cpuid.h
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1
20#ifndef __INTEL_CPUID_H__
21#define __INTEL_CPUID_H__
22
45#define CPUID_SIGNATURE 0x00
46
50#define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')
51#define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')
52#define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')
56
81#define CPUID_VERSION_INFO 0x01
82
87typedef union {
91 struct {
92 UINT32 SteppingId : 4;
93 UINT32 Model : 4;
94 UINT32 FamilyId : 4;
95 UINT32 ProcessorType : 2;
96 UINT32 Reserved1 : 2;
97 UINT32 ExtendedModelId : 4;
98 UINT32 ExtendedFamilyId : 8;
99 UINT32 Reserved2 : 4;
100 } Bits;
104 UINT32 Uint32;
106
110#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00
111#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01
112#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02
116
121typedef union {
125 struct {
130 UINT32 BrandIndex : 8;
136 UINT32 CacheLineSize : 8;
154 } Bits;
158 UINT32 Uint32;
160
165typedef union {
169 struct {
174 UINT32 SSE3 : 1;
179 UINT32 PCLMULQDQ : 1;
184 UINT32 DTES64 : 1;
189 UINT32 MONITOR : 1;
195 UINT32 DS_CPL : 1;
200 UINT32 VMX : 1;
205 UINT32 SMX : 1;
210 UINT32 EIST : 1;
215 UINT32 TM2 : 1;
221 UINT32 SSSE3 : 1;
228 UINT32 CNXT_ID : 1;
233 UINT32 SDBG : 1;
238 UINT32 FMA : 1;
243 UINT32 CMPXCHG16B : 1;
254 UINT32 PDCM : 1;
255 UINT32 Reserved : 1;
260 UINT32 PCID : 1;
265 UINT32 DCA : 1;
269 UINT32 SSE4_1 : 1;
273 UINT32 SSE4_2 : 1;
278 UINT32 x2APIC : 1;
283 UINT32 MOVBE : 1;
288 UINT32 POPCNT : 1;
293 UINT32 TSC_Deadline : 1;
298 UINT32 AESNI : 1;
304 UINT32 XSAVE : 1;
310 UINT32 OSXSAVE : 1;
315 UINT32 AVX : 1;
320 UINT32 F16C : 1;
324 UINT32 RDRAND : 1;
328 UINT32 ParaVirtualized : 1;
329 } Bits;
333 UINT32 Uint32;
335
340typedef union {
344 struct {
348 UINT32 FPU : 1;
356 UINT32 VME : 1;
362 UINT32 DE : 1;
369 UINT32 PSE : 1;
374 UINT32 TSC : 1;
380 UINT32 MSR : 1;
387 UINT32 PAE : 1;
397 UINT32 MCE : 1;
402 UINT32 CX8 : 1;
409 UINT32 APIC : 1;
410 UINT32 Reserved1 : 1;
415 UINT32 SEP : 1;
422 UINT32 MTRR : 1;
429 UINT32 PGE : 1;
436 UINT32 MCA : 1;
442 UINT32 CMOV : 1;
449 UINT32 PAT : 1;
457 UINT32 PSE_36 : 1;
462 UINT32 PSN : 1;
466 UINT32 CLFSH : 1;
467 UINT32 Reserved2 : 1;
474 UINT32 DS : 1;
481 UINT32 ACPI : 1;
486 UINT32 MMX : 1;
494 UINT32 FXSR : 1;
498 UINT32 SSE : 1;
502 UINT32 SSE2 : 1;
508 UINT32 SS : 1;
517 UINT32 HTT : 1;
522 UINT32 TM : 1;
523 UINT32 Reserved3 : 1;
531 UINT32 PBE : 1;
532 } Bits;
536 UINT32 Uint32;
538
710#define CPUID_CACHE_INFO 0x02
711
716typedef union {
720 struct {
721 UINT32 Reserved : 31;
726 UINT32 NotValid : 1;
727 } Bits;
731 UINT8 CacheDescriptor[4];
735 UINT32 Uint32;
737
764#define CPUID_SERIAL_NUMBER 0x03
765
802#define CPUID_CACHE_PARAMS 0x04
803
808typedef union {
812 struct {
817 UINT32 CacheType : 5;
821 UINT32 CacheLevel : 3;
833 UINT32 Reserved : 4;
856 } Bits;
860 UINT32 Uint32;
862
866#define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00
867#define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01
868#define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02
869#define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03
873
878typedef union {
882 struct {
887 UINT32 LineSize : 12;
892 UINT32 LinePartitions : 10;
897 UINT32 Ways : 10;
898 } Bits;
902 UINT32 Uint32;
904
909typedef union {
913 struct {
921 UINT32 Invalidate : 1;
935 UINT32 Reserved : 29;
936 } Bits;
940 UINT32 Uint32;
942
967#define CPUID_MONITOR_MWAIT 0x05
968
973typedef union {
977 struct {
983 UINT32 Reserved : 16;
984 } Bits;
988 UINT32 Uint32;
990
995typedef union {
999 struct {
1005 UINT32 Reserved : 16;
1006 } Bits;
1010 UINT32 Uint32;
1012
1017typedef union {
1021 struct {
1032 UINT32 Reserved : 30;
1033 } Bits;
1037 UINT32 Uint32;
1039
1048typedef union {
1052 struct {
1056 UINT32 C0States : 4;
1060 UINT32 C1States : 4;
1064 UINT32 C2States : 4;
1068 UINT32 C3States : 4;
1072 UINT32 C4States : 4;
1076 UINT32 C5States : 4;
1080 UINT32 C6States : 4;
1084 UINT32 C7States : 4;
1085 } Bits;
1089 UINT32 Uint32;
1091
1114#define CPUID_THERMAL_POWER_MANAGEMENT 0x06
1115
1120typedef union {
1124 struct {
1136 UINT32 ARAT : 1;
1137 UINT32 Reserved1 : 1;
1141 UINT32 PLN : 1;
1145 UINT32 ECMD : 1;
1149 UINT32 PTM : 1;
1154 UINT32 HWP : 1;
1171 UINT32 Reserved2 : 1;
1176 UINT32 HDC : 1;
1193 UINT32 FlexibleHWP : 1;
1197 UINT32 FastAccessMode : 1;
1198 UINT32 Reserved4 : 1;
1203 UINT32 Reserved5 : 11;
1204 } Bits;
1208 UINT32 Uint32;
1210
1215typedef union {
1219 struct {
1224 UINT32 Reserved : 28;
1225 } Bits;
1229 UINT32 Uint32;
1231
1236typedef union {
1240 struct {
1248 UINT32 Reserved1 : 2;
1255 UINT32 Reserved2 : 28;
1256 } Bits;
1260 UINT32 Uint32;
1262
1301#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
1302
1306#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00
1307
1313typedef union {
1317 struct {
1321 UINT32 FSGSBASE : 1;
1330 UINT32 SGX : 1;
1335 UINT32 BMI1 : 1;
1339 UINT32 HLE : 1;
1343 UINT32 AVX2 : 1;
1351 UINT32 SMEP : 1;
1357 UINT32 BMI2 : 1;
1366 UINT32 INVPCID : 1;
1370 UINT32 RTM : 1;
1375 UINT32 RDT_M : 1;
1383 UINT32 MPX : 1;
1388 UINT32 RDT_A : 1;
1392 UINT32 AVX512F : 1;
1396 UINT32 AVX512DQ : 1;
1400 UINT32 RDSEED : 1;
1405 UINT32 ADX : 1;
1410 UINT32 SMAP : 1;
1414 UINT32 AVX512_IFMA : 1;
1415 UINT32 Reserved6 : 1;
1419 UINT32 CLFLUSHOPT : 1;
1423 UINT32 CLWB : 1;
1432 UINT32 AVX512PF : 1;
1436 UINT32 AVX512ER : 1;
1440 UINT32 AVX512CD : 1;
1445 UINT32 SHA : 1;
1449 UINT32 AVX512BW : 1;
1453 UINT32 AVX512VL : 1;
1454 } Bits;
1458 UINT32 Uint32;
1460
1466typedef union {
1470 struct {
1475 UINT32 PREFETCHWT1 : 1;
1479 UINT32 AVX512_VBMI : 1;
1483 UINT32 UMIP : 1;
1487 UINT32 PKU : 1;
1492 UINT32 OSPKE : 1;
1493 UINT32 Reserved5 : 9;
1498 UINT32 Reserved7 : 1;
1502 UINT32 FiveLevelPage : 1;
1507 UINT32 MAWAU : 5;
1511 UINT32 RDPID : 1;
1512 UINT32 Reserved3 : 7;
1516 UINT32 SGX_LC : 1;
1517 UINT32 Reserved4 : 1;
1518 } Bits;
1522 UINT32 Uint32;
1524
1530typedef union {
1534 struct {
1538 UINT32 Reserved1 : 2;
1542 UINT32 AVX512_4VNNIW : 1;
1546 UINT32 AVX512_4FMAPS : 1;
1550 UINT32 Reserved4 : 11;
1554 UINT32 Hybrid : 1;
1558 UINT32 Reserved5 : 10;
1594 } Bits;
1598 UINT32 Uint32;
1600
1618#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
1619
1642#define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
1643
1648typedef union {
1652 struct {
1681 } Bits;
1685 UINT32 Uint32;
1687
1692typedef union {
1696 struct {
1725 UINT32 Reserved : 25;
1726 } Bits;
1730 UINT32 Uint32;
1732
1737typedef union {
1741 struct {
1752 UINT32 Reserved1 : 2;
1757 UINT32 Reserved2 : 16;
1758 } Bits;
1762 UINT32 Uint32;
1764
1810#define CPUID_EXTENDED_TOPOLOGY 0x0B
1811
1815typedef union {
1819 struct {
1829 UINT32 ApicIdShift : 5;
1830 UINT32 Reserved : 27;
1831 } Bits;
1835 UINT32 Uint32;
1837
1841typedef union {
1845 struct {
1858 UINT32 Reserved : 16;
1859 } Bits;
1863 UINT32 Uint32;
1865
1869typedef union {
1873 struct {
1877 UINT32 LevelNumber : 8;
1885 UINT32 LevelType : 8;
1886 UINT32 Reserved : 16;
1887 } Bits;
1891 UINT32 Uint32;
1893
1897#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
1898#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
1899#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
1903
1913#define CPUID_EXTENDED_STATE 0x0D
1914
1948#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
1949
1954typedef union {
1958 struct {
1962 UINT32 x87 : 1;
1966 UINT32 SSE : 1;
1970 UINT32 AVX : 1;
1974 UINT32 MPX : 2;
1978 UINT32 AVX_512 : 3;
1982 UINT32 IA32_XSS : 1;
1986 UINT32 PKRU : 1;
1987 UINT32 Reserved1 : 3;
1991 UINT32 IA32_XSS_2 : 1;
1992 UINT32 Reserved2 : 18;
1993 } Bits;
1997 UINT32 Uint32;
1999
2028#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
2029
2034typedef union {
2038 struct {
2042 UINT32 XSAVEOPT : 1;
2046 UINT32 XSAVEC : 1;
2050 UINT32 XGETBV : 1;
2054 UINT32 XSAVES : 1;
2055 UINT32 Reserved : 28;
2056 } Bits;
2060 UINT32 Uint32;
2062
2067typedef union {
2071 struct {
2075 UINT32 XCR0 : 1;
2079 UINT32 PT : 1;
2083 UINT32 XCR0_1 : 1;
2084 UINT32 Reserved1 : 3;
2088 UINT32 HWPState : 1;
2089 UINT32 Reserved8 : 18;
2090 } Bits;
2094 UINT32 Uint32;
2096
2142#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
2143
2148typedef union {
2152 struct {
2158 UINT32 XSS : 1;
2165 UINT32 Compacted : 1;
2166 UINT32 Reserved : 30;
2167 } Bits;
2171 UINT32 Uint32;
2173
2182#define CPUID_INTEL_RDT_MONITORING 0x0F
2183
2209#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00
2210
2216typedef union {
2220 struct {
2221 UINT32 Reserved1 : 1;
2225 UINT32 L3CacheRDT_M : 1;
2226 UINT32 Reserved2 : 30;
2227 } Bits;
2231 UINT32 Uint32;
2233
2258#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01
2259
2265typedef union {
2269 struct {
2282 UINT32 Reserved : 29;
2283 } Bits;
2287 UINT32 Uint32;
2289
2298#define CPUID_INTEL_RDT_ALLOCATION 0x10
2299
2322#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00
2323
2329typedef union {
2333 struct {
2334 UINT32 Reserved1 : 1;
2347 UINT32 Reserved3 : 28;
2348 } Bits;
2352 UINT32 Uint32;
2354
2382#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
2383
2389typedef union {
2393 struct {
2398 UINT32 CapacityLength : 5;
2399 UINT32 Reserved : 27;
2400 } Bits;
2404 UINT32 Uint32;
2406
2412typedef union {
2416 struct {
2417 UINT32 Reserved3 : 2;
2422 UINT32 Reserved2 : 29;
2423 } Bits;
2427 UINT32 Uint32;
2429
2435typedef union {
2439 struct {
2443 UINT32 HighestCosNumber : 16;
2444 UINT32 Reserved : 16;
2445 } Bits;
2449 UINT32 Uint32;
2451
2477#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02
2478
2484typedef union {
2488 struct {
2493 UINT32 CapacityLength : 5;
2494 UINT32 Reserved : 27;
2495 } Bits;
2499 UINT32 Uint32;
2501
2507typedef union {
2511 struct {
2515 UINT32 HighestCosNumber : 16;
2516 UINT32 Reserved : 16;
2517 } Bits;
2521 UINT32 Uint32;
2523
2555#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03
2556
2562typedef union {
2566 struct {
2572 UINT32 Reserved : 20;
2573 } Bits;
2577 UINT32 Uint32;
2579
2585typedef union {
2589 struct {
2593 UINT32 Reserved1 : 2;
2597 UINT32 Liner : 1;
2598 UINT32 Reserved2 : 29;
2599 } Bits;
2603 UINT32 Uint32;
2605
2611typedef union {
2615 struct {
2619 UINT32 HighestCosNumber : 16;
2620 UINT32 Reserved : 16;
2621 } Bits;
2625 UINT32 Uint32;
2627
2643#define CPUID_INTEL_SGX 0x12
2644
2672#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
2673
2678typedef union {
2682 struct {
2686 UINT32 SGX1 : 1;
2690 UINT32 SGX2 : 1;
2691 UINT32 Reserved1 : 3;
2696 UINT32 ENCLV : 1;
2701 UINT32 ENCLS : 1;
2702 UINT32 Reserved2 : 25;
2703 } Bits;
2707 UINT32 Uint32;
2709
2714typedef union {
2718 struct {
2729 UINT32 Reserved : 16;
2730 } Bits;
2734 UINT32 Uint32;
2736
2771#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
2772
2806#define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02
2807
2812typedef union {
2816 struct {
2824 UINT32 SubLeafType : 4;
2825 UINT32 Reserved : 8;
2831 } Bits;
2835 UINT32 Uint32;
2837
2842typedef union {
2846 struct {
2852 UINT32 Reserved : 12;
2853 } Bits;
2857 UINT32 Uint32;
2859
2864typedef union {
2868 struct {
2875 UINT32 EpcSection : 4;
2876 UINT32 Reserved : 8;
2882 } Bits;
2886 UINT32 Uint32;
2888
2893typedef union {
2897 struct {
2903 UINT32 Reserved : 12;
2904 } Bits;
2908 UINT32 Uint32;
2910
2919#define CPUID_INTEL_PROCESSOR_TRACE 0x14
2920
2946#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
2947
2952typedef union {
2956 struct {
2961 UINT32 Cr3Filter : 1;
2976 UINT32 Mtc : 1;
2982 UINT32 PTWrite : 1;
2989 UINT32 Reserved : 26;
2990 } Bits;
2994 UINT32 Uint32;
2996
3001typedef union {
3005 struct {
3011 UINT32 RTIT : 1;
3017 UINT32 ToPA : 1;
3026 UINT32 Reserved : 27;
3031 UINT32 LIP : 1;
3032 } Bits;
3036 UINT32 Uint32;
3038
3072#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
3073
3078typedef union {
3082 struct {
3087 UINT32 Reserved : 13;
3092 } Bits;
3096 UINT32 Uint32;
3098
3103typedef union {
3107 struct {
3116 } Bits;
3120 UINT32 Uint32;
3122
3154#define CPUID_TIME_STAMP_COUNTER 0x15
3155
3189#define CPUID_PROCESSOR_FREQUENCY 0x16
3190
3195typedef union {
3199 struct {
3204 UINT32 Reserved : 16;
3205 } Bits;
3209 UINT32 Uint32;
3211
3216typedef union {
3220 struct {
3224 UINT32 MaximumFrequency : 16;
3225 UINT32 Reserved : 16;
3226 } Bits;
3230 UINT32 Uint32;
3232
3237typedef union {
3241 struct {
3245 UINT32 BusFrequency : 16;
3246 UINT32 Reserved : 16;
3247 } Bits;
3251 UINT32 Uint32;
3253
3270#define CPUID_SOC_VENDOR 0x17
3271
3300#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
3301
3306typedef union {
3310 struct {
3314 UINT32 SocVendorId : 16;
3320 UINT32 IsVendorScheme : 1;
3321 UINT32 Reserved : 15;
3322 } Bits;
3326 UINT32 Uint32;
3328
3357#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
3358
3363typedef union {
3367 CHAR8 BrandString[4];
3371 UINT32 Uint32;
3373
3402#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
3403
3432#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
3433
3457#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18
3458
3486#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00
3487
3491typedef union {
3495 struct {
3499 UINT32 Page4K : 1;
3503 UINT32 Page2M : 1;
3507 UINT32 Page4M : 1;
3511 UINT32 Page1G : 1;
3515 UINT32 Reserved1 : 4;
3520 UINT32 Partitioning : 3;
3524 UINT32 Reserved2 : 5;
3528 UINT32 Way : 16;
3529 } Bits;
3533 UINT32 Uint32;
3535
3539typedef union {
3543 struct {
3559 UINT32 Reserved1 : 5;
3564 UINT32 MaximumNum : 12;
3568 UINT32 Reserved2 : 6;
3569 } Bits;
3573 UINT32 Uint32;
3575
3579#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID 0x00
3580#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB 0x01
3581#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB 0x02
3582#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB 0x03
3586
3611#define CPUID_HYBRID_INFORMATION 0x1A
3612
3616#define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00
3617
3622typedef union {
3626 struct {
3635 UINT32 NativeModelId : 24;
3639 UINT32 CoreType : 8;
3640 } Bits;
3644 UINT32 Uint32;
3646
3650#define CPUID_CORE_TYPE_INTEL_ATOM 0x20
3651#define CPUID_CORE_TYPE_INTEL_CORE 0x40
3655
3680#define CPUID_V2_EXTENDED_TOPOLOGY 0x1F
3681
3687#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03
3688#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04
3689#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05
3693
3711#define CPUID_GUESTTD_RUNTIME_ENVIRONMENT 0x21
3712
3716#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('I', 'n', 't', 'e')
3717#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 (' ', ' ', ' ', ' ')
3718#define CPUID_GUESTTD_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('l', 'T', 'D', 'X')
3722
3740#define CPUID_EXTENDED_FUNCTION 0x80000000
3741
3763#define CPUID_EXTENDED_CPU_SIG 0x80000001
3764
3769typedef union {
3773 struct {
3777 UINT32 LAHF_SAHF : 1;
3778 UINT32 Reserved1 : 4;
3782 UINT32 LZCNT : 1;
3783 UINT32 Reserved2 : 2;
3787 UINT32 PREFETCHW : 1;
3788 UINT32 Reserved3 : 23;
3789 } Bits;
3793 UINT32 Uint32;
3795
3800typedef union {
3804 struct {
3805 UINT32 Reserved1 : 11;
3809 UINT32 SYSCALL_SYSRET : 1;
3810 UINT32 Reserved2 : 8;
3814 UINT32 NX : 1;
3815 UINT32 Reserved3 : 5;
3819 UINT32 Page1GB : 1;
3823 UINT32 RDTSCP : 1;
3824 UINT32 Reserved4 : 1;
3828 UINT32 LM : 1;
3829 UINT32 Reserved5 : 2;
3830 } Bits;
3834 UINT32 Uint32;
3836
3857#define CPUID_BRAND_STRING1 0x80000002
3858
3863typedef union {
3867 CHAR8 BrandString[4];
3871 UINT32 Uint32;
3873
3894#define CPUID_BRAND_STRING2 0x80000003
3895
3916#define CPUID_BRAND_STRING3 0x80000004
3917
3936#define CPUID_EXTENDED_CACHE_INFO 0x80000006
3937
3941typedef union {
3945 struct {
3949 UINT32 CacheLineSize : 8;
3950 UINT32 Reserved : 4;
3960 UINT32 CacheSize : 16;
3961 } Bits;
3965 UINT32 Uint32;
3967
3971#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00
3972#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01
3973#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02
3974#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04
3975#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06
3976#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08
3977#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY 0x0A
3978#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY 0x0B
3979#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY 0x0C
3980#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY 0x0D
3981#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY 0x0E
3982#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F
3986
4005#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
4006
4011typedef union {
4015 struct {
4016 UINT32 Reserved1 : 8;
4020 UINT32 InvariantTsc : 1;
4021 UINT32 Reserved2 : 23;
4022 } Bits;
4026 UINT32 Uint32;
4028
4047#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
4048
4053typedef union {
4057 struct {
4070 UINT32 Reserved : 16;
4071 } Bits;
4075 UINT32 Uint32;
4077
4078#endif
UINT32 SelfInitializingCache
Definition: Cpuid.h:825
UINT32 MaximumAddressableIdsForLogicalProcessors
Definition: Cpuid.h:843
UINT32 FullyAssociativeCache
Definition: Cpuid.h:829
UINT32 MaximumAddressableIdsForProcessorCores
Definition: Cpuid.h:855
UINT32 LinePartitions
Definition: Cpuid.h:892
UINT32 CacheInclusiveness
Definition: Cpuid.h:927
UINT32 ComplexCacheIndexing
Definition: Cpuid.h:934
UINT32 SmallestMonitorLineSize
Definition: Cpuid.h:982
UINT32 LargestMonitorLineSize
Definition: Cpuid.h:1004
UINT32 ExtensionsSupported
Definition: Cpuid.h:1026
UINT32 Reserved1
[Bits 15:14] Reserved
Definition: Cpuid.h:96
UINT32 ProcessorType
[Bits 13:12] Processor Type
Definition: Cpuid.h:95
UINT32 Reserved2
Reserved.
Definition: Cpuid.h:99
UINT32 ExtendedModelId
[Bits 19:16] Extended Model ID
Definition: Cpuid.h:97
UINT32 FamilyId
[Bits 11:8] Family
Definition: Cpuid.h:94
UINT32 Model
[Bits 7:4] Model
Definition: Cpuid.h:93
UINT32 SteppingId
[Bits 3:0] Stepping ID
Definition: Cpuid.h:92
UINT32 ExtendedFamilyId
[Bits 27:20] Extended Family ID
Definition: Cpuid.h:98
UINT32 MaximumAddressableIdsForLogicalProcessors
Definition: Cpuid.h:147
UINT32 CacheLineSize
Definition: Cpuid.h:136
UINT32 InitialLocalApicId
Definition: Cpuid.h:153
UINT32 xTPR_Update_Control
Definition: Cpuid.h:248
UINT32 ParaVirtualized
Definition: Cpuid.h:328