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LocalApic.h
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1
9#ifndef __INTEL_LOCAL_APIC_H__
10#define __INTEL_LOCAL_APIC_H__
11
12//
13// Definition for Local APIC registers and related values
14//
15#define XAPIC_ID_OFFSET 0x20
16#define XAPIC_VERSION_OFFSET 0x30
17#define XAPIC_EOI_OFFSET 0x0b0
18#define XAPIC_ICR_DFR_OFFSET 0x0e0
19#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
20#define XAPIC_ICR_LOW_OFFSET 0x300
21#define XAPIC_ICR_HIGH_OFFSET 0x310
22#define XAPIC_LVT_TIMER_OFFSET 0x320
23#define XAPIC_LVT_LINT0_OFFSET 0x350
24#define XAPIC_LVT_LINT1_OFFSET 0x360
25#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
26#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
27#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
28
29#define X2APIC_MSR_BASE_ADDRESS 0x800
30#define X2APIC_MSR_ICR_ADDRESS 0x830
31
32#define LOCAL_APIC_DELIVERY_MODE_FIXED 0
33#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
34#define LOCAL_APIC_DELIVERY_MODE_SMI 2
35#define LOCAL_APIC_DELIVERY_MODE_NMI 4
36#define LOCAL_APIC_DELIVERY_MODE_INIT 5
37#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
38#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
39
40#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0
41#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
42#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
43#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
44
45//
46// Local APIC Version Register.
47//
48typedef union {
49 struct {
50 UINT32 Version : 8;
51 UINT32 Reserved0 : 8;
52 UINT32 MaxLvtEntry : 8;
54 UINT32 Reserved1 : 7;
55 } Bits;
56 UINT32 Uint32;
58
59//
60// Low half of Interrupt Command Register (ICR).
61//
62typedef union {
63 struct {
64 UINT32 Vector : 8;
65 UINT32 DeliveryMode : 3;
66 UINT32 DestinationMode : 1;
67 UINT32 DeliveryStatus : 1;
68 UINT32 Reserved0 : 1;
69 UINT32 Level : 1;
70 UINT32 TriggerMode : 1;
71 UINT32 Reserved1 : 2;
73 UINT32 Reserved2 : 12;
74 } Bits;
75 UINT32 Uint32;
77
78//
79// High half of Interrupt Command Register (ICR)
80//
81typedef union {
82 struct {
83 UINT32 Reserved0 : 24;
84 UINT32 Destination : 8;
85 } Bits;
86 UINT32 Uint32;
88
89//
90// Spurious-Interrupt Vector Register (SVR)
91//
92typedef union {
93 struct {
94 UINT32 SpuriousVector : 8;
95 UINT32 SoftwareEnable : 1;
97 UINT32 Reserved0 : 2;
99 UINT32 Reserved1 : 19;
100 } Bits;
101 UINT32 Uint32;
103
104//
105// Divide Configuration Register (DCR)
106//
107typedef union {
108 struct {
109 UINT32 DivideValue1 : 2;
110 UINT32 Reserved0 : 1;
111 UINT32 DivideValue2 : 1;
112 UINT32 Reserved1 : 28;
113 } Bits;
114 UINT32 Uint32;
116
117//
118// LVT Timer Register
119//
120typedef union {
121 struct {
122 UINT32 Vector : 8;
123 UINT32 Reserved0 : 4;
124 UINT32 DeliveryStatus : 1;
125 UINT32 Reserved1 : 3;
126 UINT32 Mask : 1;
127 UINT32 TimerMode : 1;
128 UINT32 Reserved2 : 14;
129 } Bits;
130 UINT32 Uint32;
132
133//
134// LVT LINT0/LINT1 Register
135//
136typedef union {
137 struct {
138 UINT32 Vector : 8;
139 UINT32 DeliveryMode : 3;
140 UINT32 Reserved0 : 1;
141 UINT32 DeliveryStatus : 1;
142 UINT32 InputPinPolarity : 1;
143 UINT32 RemoteIrr : 1;
144 UINT32 TriggerMode : 1;
145 UINT32 Mask : 1;
146 UINT32 Reserved1 : 15;
147 } Bits;
148 UINT32 Uint32;
150
151//
152// MSI Address Register
153//
154typedef union {
155 struct {
156 UINT32 Reserved0 : 2;
157 UINT32 DestinationMode : 1;
158 UINT32 RedirectionHint : 1;
159 UINT32 Reserved1 : 8;
160 UINT32 DestinationId : 8;
161 UINT32 BaseAddress : 12;
162 } Bits;
163 UINT32 Uint32;
165
166//
167// MSI Address Register
168//
169typedef union {
170 struct {
171 UINT32 Vector : 8;
172 UINT32 DeliveryMode : 3;
173 UINT32 Reserved0 : 3;
174 UINT32 Level : 1;
175 UINT32 TriggerMode : 1;
176 UINT32 Reserved1 : 16;
177 UINT32 Reserved2 : 32;
178 } Bits;
179 UINT64 Uint64;
181
182#endif
UINT32 DivideValue1
Low 2 bits of the divide value.
Definition: LocalApic.h:109
UINT32 Reserved0
Always 0.
Definition: LocalApic.h:110
UINT32 DivideValue2
Highest 1 bit of the divide value.
Definition: LocalApic.h:111
UINT32 Reserved1
Reserved.
Definition: LocalApic.h:112
UINT32 Reserved0
Reserved.
Definition: LocalApic.h:83
UINT32 Destination
Specifies the target processor or processors in xAPIC mode.
Definition: LocalApic.h:84
UINT32 Uint32
Destination field expanded to 32-bit in x2APIC mode.
Definition: LocalApic.h:86
UINT32 TriggerMode
0: edge, 1: level when using the INIT level de-assert delivery mode.
Definition: LocalApic.h:70
UINT32 DestinationMode
0: physical destination mode, 1: logical destination mode.
Definition: LocalApic.h:66
UINT32 Vector
The vector number of the interrupt being sent.
Definition: LocalApic.h:64
UINT32 DeliveryMode
Specifies the type of IPI to be sent.
Definition: LocalApic.h:65
UINT32 Reserved1
Reserved.
Definition: LocalApic.h:71
UINT32 Level
0 for the INIT level de-assert delivery mode. Otherwise 1.
Definition: LocalApic.h:69
UINT32 Reserved2
Reserved.
Definition: LocalApic.h:73
UINT32 DestinationShorthand
A shorthand notation to specify the destination of the interrupt.
Definition: LocalApic.h:72
UINT32 Reserved0
Reserved.
Definition: LocalApic.h:68
UINT32 DeliveryStatus
Indicates the IPI delivery status. This field is reserved in x2APIC mode.
Definition: LocalApic.h:67
UINT32 Reserved1
Reserved.
Definition: LocalApic.h:146
UINT32 Reserved0
Reserved.
Definition: LocalApic.h:140
UINT32 TriggerMode
0:edge, 1:level.
Definition: LocalApic.h:144
UINT32 InputPinPolarity
Interrupt Input Pin Polarity.
Definition: LocalApic.h:142
UINT32 RemoteIrr
RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
Definition: LocalApic.h:143
UINT32 DeliveryMode
Specifies the type of interrupt to be sent.
Definition: LocalApic.h:139
UINT32 Mask
0: Not masked, 1: Masked.
Definition: LocalApic.h:145
UINT32 DeliveryStatus
0: Idle, 1: send pending.
Definition: LocalApic.h:141
UINT32 Vector
The vector number of the interrupt being sent.
Definition: LocalApic.h:138
UINT32 Reserved2
Reserved.
Definition: LocalApic.h:128
UINT32 Reserved0
Reserved.
Definition: LocalApic.h:123
UINT32 Vector
The vector number of the interrupt being sent.
Definition: LocalApic.h:122
UINT32 TimerMode
0: One-shot, 1: Periodic.
Definition: LocalApic.h:127
UINT32 DeliveryStatus
0: Idle, 1: send pending.
Definition: LocalApic.h:124
UINT32 Mask
0: Not masked, 1: Masked.
Definition: LocalApic.h:126
UINT32 Reserved1
Reserved.
Definition: LocalApic.h:125
UINT32 Reserved1
Reserved.
Definition: LocalApic.h:159
UINT32 RedirectionHint
Specifies the Redirection Hint.
Definition: LocalApic.h:158
UINT32 BaseAddress
Must be 0FEEH.
Definition: LocalApic.h:161
UINT32 Reserved0
Reserved.
Definition: LocalApic.h:156
UINT32 DestinationMode
Specifies the Destination Mode.
Definition: LocalApic.h:157
UINT32 DestinationId
Specifies the Destination ID.
Definition: LocalApic.h:160
UINT32 Reserved2
Reserved.
Definition: LocalApic.h:177
UINT32 DeliveryMode
Specifies the type of interrupt to be sent.
Definition: LocalApic.h:172
UINT32 Level
0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
Definition: LocalApic.h:174
UINT32 TriggerMode
0:Edge, 1:Level.
Definition: LocalApic.h:175
UINT32 Reserved1
Reserved.
Definition: LocalApic.h:176
UINT32 Vector
Interrupt vector in range 010h..0FEH.
Definition: LocalApic.h:171
UINT32 Reserved0
Reserved.
Definition: LocalApic.h:173
UINT32 SpuriousVector
Spurious Vector.
Definition: LocalApic.h:94
UINT32 SoftwareEnable
APIC Software Enable/Disable.
Definition: LocalApic.h:95
UINT32 FocusProcessorChecking
Focus Processor Checking.
Definition: LocalApic.h:96
UINT32 Reserved0
Reserved.
Definition: LocalApic.h:97
UINT32 Reserved1
Reserved.
Definition: LocalApic.h:99
UINT32 EoiBroadcastSuppression
EOI-Broadcast Suppression.
Definition: LocalApic.h:98
UINT32 MaxLvtEntry
Number of LVT entries minus 1.
Definition: LocalApic.h:52
UINT32 Reserved0
Reserved.
Definition: LocalApic.h:51
UINT32 Reserved1
Reserved.
Definition: LocalApic.h:54
UINT32 Version
The version numbers of the local APIC.
Definition: LocalApic.h:50
UINT32 EoiBroadcastSuppression
1 if EOI-broadcast suppression supported.
Definition: LocalApic.h:53