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PciExpressLib.c
Go to the documentation of this file.
1
13#include <PiDxe.h>
14
15#include <Guid/EventGroup.h>
16
17#include <Library/BaseLib.h>
19#include <Library/IoLib.h>
20#include <Library/DebugLib.h>
21#include <Library/PcdLib.h>
26
34#define ASSERT_INVALID_PCI_ADDRESS(A) \
35 ASSERT (((A) & ~0xfffffff) == 0)
36
40typedef struct {
41 UINTN PhysicalAddress;
42 UINTN VirtualAddress;
44
49
54UINTN mDxeRuntimePciExpressLibPciExpressBaseSize = 0;
55
60
65
70
78VOID
79EFIAPI
81 IN EFI_EVENT Event,
82 IN VOID *Context
83 )
84{
85 UINTN Index;
86
87 //
88 // If there have been no runtime registrations, then just return
89 //
91 return;
92 }
93
94 //
95 // Convert physical addresses associated with the set of registered PCI devices to
96 // virtual addresses.
97 //
98 for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {
99 EfiConvertPointer (0, (VOID **)&(mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress));
100 }
101
102 //
103 // Convert table pointer that is allocated from EfiRuntimeServicesData to a virtual address.
104 //
106}
107
120EFIAPI
122 IN EFI_HANDLE ImageHandle,
123 IN EFI_SYSTEM_TABLE *SystemTable
124 )
125{
126 EFI_STATUS Status;
127
128 //
129 // Cache the physical address of the PCI Express MMIO range into a module global variable
130 //
132 mDxeRuntimePciExpressLibPciExpressBaseSize = (UINTN)PcdGet64 (PcdPciExpressBaseSize);
133
134 //
135 // Register SetVirtualAddressMap () notify function
136 //
137 Status = gBS->CreateEvent (
138 EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE,
139 TPL_NOTIFY,
141 NULL,
143 );
144 ASSERT_EFI_ERROR (Status);
145
146 return Status;
147}
148
161EFIAPI
163 IN EFI_HANDLE ImageHandle,
164 IN EFI_SYSTEM_TABLE *SystemTable
165 )
166{
167 EFI_STATUS Status;
168
169 //
170 // If one or more PCI devices have been registered for runtime access, then
171 // free the registration table.
172 //
175 }
176
177 //
178 // Close the Set Virtual Address Map event
179 //
180 Status = gBS->CloseEvent (mDxeRuntimePciExpressLibVirtualNotifyEvent);
181 ASSERT_EFI_ERROR (Status);
182
183 return Status;
184}
185
200UINTN
202 IN UINTN Address
203 )
204{
205 UINTN Index;
206
207 //
208 // Make sure Address is valid
209 //
211
212 //
213 // Make sure the Address is in MMCONF address space
214 //
215 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
216 return (UINTN)-1;
217 }
218
219 //
220 // Convert Address to a physical address in the MMIO PCI Express range
221 //
223
224 //
225 // If SetVirtualAddressMap() has not been called, then just return the physical address
226 //
227 if (!EfiGoneVirtual ()) {
228 return Address;
229 }
230
231 //
232 // See if there is a physical address match at the exact same index as the last address match
233 //
234 if (mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].PhysicalAddress == (Address & (~0x00000fff))) {
235 //
236 // Convert the physical address to a virtual address and return the virtual address
237 //
238 return (Address & 0x00000fff) + mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].VirtualAddress;
239 }
240
241 //
242 // Search the entire table for a physical address match
243 //
244 for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {
245 if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == (Address & (~0x00000fff))) {
246 //
247 // Cache the matching index value
248 //
250 //
251 // Convert the physical address to a virtual address and return the virtual address
252 //
253 return (Address & 0x00000fff) + mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress;
254 }
255 }
256
257 //
258 // No match was found. This is a critical error at OS runtime, so ASSERT() and force a breakpoint.
259 //
260 CpuBreakpoint ();
261
262 //
263 // Return the physical address
264 //
265 return Address;
266}
267
290RETURN_STATUS
291EFIAPI
293 IN UINTN Address
294 )
295{
296 EFI_STATUS Status;
298 UINTN Index;
299 VOID *NewTable;
300
301 //
302 // Return an error if this function is called after ExitBootServices().
303 //
304 if (EfiAtRuntime ()) {
305 return RETURN_UNSUPPORTED;
306 }
307
308 //
309 // Make sure Address is valid
310 //
312
313 //
314 // Make sure the Address is in MMCONF address space
315 //
316 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
317 return RETURN_UNSUPPORTED;
318 }
319
320 //
321 // Convert Address to a physical address in the MMIO PCI Express range
322 // at the beginning of the PCI Configuration header for the specified
323 // PCI Bus/Dev/Func
324 //
325 Address = GetPciExpressAddress (Address & 0x0ffff000);
326
327 //
328 // See if Address has already been registered for runtime access
329 //
330 for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {
331 if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == Address) {
332 return RETURN_SUCCESS;
333 }
334 }
335
336 //
337 // Get the GCD Memory Descriptor for the PCI Express Bus/Dev/Func specified by Address
338 //
339 Status = gDS->GetMemorySpaceDescriptor (Address, &Descriptor);
340 if (EFI_ERROR (Status)) {
341 return RETURN_UNSUPPORTED;
342 }
343
344 //
345 // Mark the 4KB region for the PCI Express Bus/Dev/Func as EFI_RUNTIME_MEMORY so the OS
346 // will allocate a virtual address range for the 4KB PCI Configuration Header.
347 //
348 Status = gDS->SetMemorySpaceAttributes (Address, 0x1000, Descriptor.Attributes | EFI_MEMORY_RUNTIME);
349 if (EFI_ERROR (Status)) {
350 return RETURN_UNSUPPORTED;
351 }
352
353 //
354 // Grow the size of the registration table
355 //
356 NewTable = ReallocateRuntimePool (
360 );
361 if (NewTable == NULL) {
363 }
364
369
370 return RETURN_SUCCESS;
371}
372
388UINT8
389EFIAPI
391 IN UINTN Address
392 )
393{
395 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
396 return (UINT8)-1;
397 }
398
399 return MmioRead8 (GetPciExpressAddress (Address));
400}
401
419UINT8
420EFIAPI
422 IN UINTN Address,
423 IN UINT8 Value
424 )
425{
426 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
427 return (UINT8)-1;
428 }
429
430 return MmioWrite8 (GetPciExpressAddress (Address), Value);
431}
432
454UINT8
455EFIAPI
457 IN UINTN Address,
458 IN UINT8 OrData
459 )
460{
461 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
462 return (UINT8)-1;
463 }
464
465 return MmioOr8 (GetPciExpressAddress (Address), OrData);
466}
467
489UINT8
490EFIAPI
492 IN UINTN Address,
493 IN UINT8 AndData
494 )
495{
496 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
497 return (UINT8)-1;
498 }
499
500 return MmioAnd8 (GetPciExpressAddress (Address), AndData);
501}
502
526UINT8
527EFIAPI
529 IN UINTN Address,
530 IN UINT8 AndData,
531 IN UINT8 OrData
532 )
533{
534 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
535 return (UINT8)-1;
536 }
537
538 return MmioAndThenOr8 (
539 GetPciExpressAddress (Address),
540 AndData,
541 OrData
542 );
543}
544
567UINT8
568EFIAPI
570 IN UINTN Address,
571 IN UINTN StartBit,
572 IN UINTN EndBit
573 )
574{
575 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
576 return (UINT8)-1;
577 }
578
579 return MmioBitFieldRead8 (
580 GetPciExpressAddress (Address),
581 StartBit,
582 EndBit
583 );
584}
585
611UINT8
612EFIAPI
614 IN UINTN Address,
615 IN UINTN StartBit,
616 IN UINTN EndBit,
617 IN UINT8 Value
618 )
619{
620 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
621 return (UINT8)-1;
622 }
623
624 return MmioBitFieldWrite8 (
625 GetPciExpressAddress (Address),
626 StartBit,
627 EndBit,
628 Value
629 );
630}
631
660UINT8
661EFIAPI
663 IN UINTN Address,
664 IN UINTN StartBit,
665 IN UINTN EndBit,
666 IN UINT8 OrData
667 )
668{
669 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
670 return (UINT8)-1;
671 }
672
673 return MmioBitFieldOr8 (
674 GetPciExpressAddress (Address),
675 StartBit,
676 EndBit,
677 OrData
678 );
679}
680
709UINT8
710EFIAPI
712 IN UINTN Address,
713 IN UINTN StartBit,
714 IN UINTN EndBit,
715 IN UINT8 AndData
716 )
717{
718 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
719 return (UINT8)-1;
720 }
721
722 return MmioBitFieldAnd8 (
723 GetPciExpressAddress (Address),
724 StartBit,
725 EndBit,
726 AndData
727 );
728}
729
762UINT8
763EFIAPI
765 IN UINTN Address,
766 IN UINTN StartBit,
767 IN UINTN EndBit,
768 IN UINT8 AndData,
769 IN UINT8 OrData
770 )
771{
772 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
773 return (UINT8)-1;
774 }
775
777 GetPciExpressAddress (Address),
778 StartBit,
779 EndBit,
780 AndData,
781 OrData
782 );
783}
784
802UINT16
803EFIAPI
805 IN UINTN Address
806 )
807{
808 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
809 return (UINT16)-1;
810 }
811
812 return MmioRead16 (GetPciExpressAddress (Address));
813}
814
833UINT16
834EFIAPI
836 IN UINTN Address,
837 IN UINT16 Value
838 )
839{
840 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
841 return (UINT16)-1;
842 }
843
844 return MmioWrite16 (GetPciExpressAddress (Address), Value);
845}
846
869UINT16
870EFIAPI
872 IN UINTN Address,
873 IN UINT16 OrData
874 )
875{
876 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
877 return (UINT16)-1;
878 }
879
880 return MmioOr16 (GetPciExpressAddress (Address), OrData);
881}
882
905UINT16
906EFIAPI
908 IN UINTN Address,
909 IN UINT16 AndData
910 )
911{
912 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
913 return (UINT16)-1;
914 }
915
916 return MmioAnd16 (GetPciExpressAddress (Address), AndData);
917}
918
943UINT16
944EFIAPI
946 IN UINTN Address,
947 IN UINT16 AndData,
948 IN UINT16 OrData
949 )
950{
951 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
952 return (UINT16)-1;
953 }
954
955 return MmioAndThenOr16 (
956 GetPciExpressAddress (Address),
957 AndData,
958 OrData
959 );
960}
961
985UINT16
986EFIAPI
988 IN UINTN Address,
989 IN UINTN StartBit,
990 IN UINTN EndBit
991 )
992{
993 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
994 return (UINT16)-1;
995 }
996
997 return MmioBitFieldRead16 (
998 GetPciExpressAddress (Address),
999 StartBit,
1000 EndBit
1001 );
1002}
1003
1030UINT16
1031EFIAPI
1033 IN UINTN Address,
1034 IN UINTN StartBit,
1035 IN UINTN EndBit,
1036 IN UINT16 Value
1037 )
1038{
1039 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1040 return (UINT16)-1;
1041 }
1042
1043 return MmioBitFieldWrite16 (
1044 GetPciExpressAddress (Address),
1045 StartBit,
1046 EndBit,
1047 Value
1048 );
1049}
1050
1080UINT16
1081EFIAPI
1083 IN UINTN Address,
1084 IN UINTN StartBit,
1085 IN UINTN EndBit,
1086 IN UINT16 OrData
1087 )
1088{
1089 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1090 return (UINT16)-1;
1091 }
1092
1093 return MmioBitFieldOr16 (
1094 GetPciExpressAddress (Address),
1095 StartBit,
1096 EndBit,
1097 OrData
1098 );
1099}
1100
1130UINT16
1131EFIAPI
1133 IN UINTN Address,
1134 IN UINTN StartBit,
1135 IN UINTN EndBit,
1136 IN UINT16 AndData
1137 )
1138{
1139 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1140 return (UINT16)-1;
1141 }
1142
1143 return MmioBitFieldAnd16 (
1144 GetPciExpressAddress (Address),
1145 StartBit,
1146 EndBit,
1147 AndData
1148 );
1149}
1150
1184UINT16
1185EFIAPI
1187 IN UINTN Address,
1188 IN UINTN StartBit,
1189 IN UINTN EndBit,
1190 IN UINT16 AndData,
1191 IN UINT16 OrData
1192 )
1193{
1194 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1195 return (UINT16)-1;
1196 }
1197
1199 GetPciExpressAddress (Address),
1200 StartBit,
1201 EndBit,
1202 AndData,
1203 OrData
1204 );
1205}
1206
1224UINT32
1225EFIAPI
1227 IN UINTN Address
1228 )
1229{
1230 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1231 return (UINT32)-1;
1232 }
1233
1234 return MmioRead32 (GetPciExpressAddress (Address));
1235}
1236
1255UINT32
1256EFIAPI
1258 IN UINTN Address,
1259 IN UINT32 Value
1260 )
1261{
1262 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1263 return (UINT32)-1;
1264 }
1265
1266 return MmioWrite32 (GetPciExpressAddress (Address), Value);
1267}
1268
1291UINT32
1292EFIAPI
1294 IN UINTN Address,
1295 IN UINT32 OrData
1296 )
1297{
1298 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1299 return (UINT32)-1;
1300 }
1301
1302 return MmioOr32 (GetPciExpressAddress (Address), OrData);
1303}
1304
1327UINT32
1328EFIAPI
1330 IN UINTN Address,
1331 IN UINT32 AndData
1332 )
1333{
1334 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1335 return (UINT32)-1;
1336 }
1337
1338 return MmioAnd32 (GetPciExpressAddress (Address), AndData);
1339}
1340
1365UINT32
1366EFIAPI
1368 IN UINTN Address,
1369 IN UINT32 AndData,
1370 IN UINT32 OrData
1371 )
1372{
1373 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1374 return (UINT32)-1;
1375 }
1376
1377 return MmioAndThenOr32 (
1378 GetPciExpressAddress (Address),
1379 AndData,
1380 OrData
1381 );
1382}
1383
1407UINT32
1408EFIAPI
1410 IN UINTN Address,
1411 IN UINTN StartBit,
1412 IN UINTN EndBit
1413 )
1414{
1415 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1416 return (UINT32)-1;
1417 }
1418
1419 return MmioBitFieldRead32 (
1420 GetPciExpressAddress (Address),
1421 StartBit,
1422 EndBit
1423 );
1424}
1425
1452UINT32
1453EFIAPI
1455 IN UINTN Address,
1456 IN UINTN StartBit,
1457 IN UINTN EndBit,
1458 IN UINT32 Value
1459 )
1460{
1461 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1462 return (UINT32)-1;
1463 }
1464
1465 return MmioBitFieldWrite32 (
1466 GetPciExpressAddress (Address),
1467 StartBit,
1468 EndBit,
1469 Value
1470 );
1471}
1472
1502UINT32
1503EFIAPI
1505 IN UINTN Address,
1506 IN UINTN StartBit,
1507 IN UINTN EndBit,
1508 IN UINT32 OrData
1509 )
1510{
1511 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1512 return (UINT32)-1;
1513 }
1514
1515 return MmioBitFieldOr32 (
1516 GetPciExpressAddress (Address),
1517 StartBit,
1518 EndBit,
1519 OrData
1520 );
1521}
1522
1552UINT32
1553EFIAPI
1555 IN UINTN Address,
1556 IN UINTN StartBit,
1557 IN UINTN EndBit,
1558 IN UINT32 AndData
1559 )
1560{
1561 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1562 return (UINT32)-1;
1563 }
1564
1565 return MmioBitFieldAnd32 (
1566 GetPciExpressAddress (Address),
1567 StartBit,
1568 EndBit,
1569 AndData
1570 );
1571}
1572
1606UINT32
1607EFIAPI
1609 IN UINTN Address,
1610 IN UINTN StartBit,
1611 IN UINTN EndBit,
1612 IN UINT32 AndData,
1613 IN UINT32 OrData
1614 )
1615{
1616 if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1617 return (UINT32)-1;
1618 }
1619
1621 GetPciExpressAddress (Address),
1622 StartBit,
1623 EndBit,
1624 AndData,
1625 OrData
1626 );
1627}
1628
1653UINTN
1654EFIAPI
1656 IN UINTN StartAddress,
1657 IN UINTN Size,
1658 OUT VOID *Buffer
1659 )
1660{
1661 UINTN ReturnValue;
1662
1663 //
1664 // Make sure Address is valid
1665 //
1666 ASSERT_INVALID_PCI_ADDRESS (StartAddress);
1667 ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
1668
1669 //
1670 // Make sure the Address is in MMCONF address space
1671 //
1672 if (StartAddress >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1673 return (UINTN)-1;
1674 }
1675
1676 if (Size == 0) {
1677 return Size;
1678 }
1679
1680 ASSERT (Buffer != NULL);
1681
1682 //
1683 // Save Size for return
1684 //
1685 ReturnValue = Size;
1686
1687 if ((StartAddress & 1) != 0) {
1688 //
1689 // Read a byte if StartAddress is byte aligned
1690 //
1691 *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
1692 StartAddress += sizeof (UINT8);
1693 Size -= sizeof (UINT8);
1694 Buffer = (UINT8 *)Buffer + 1;
1695 }
1696
1697 if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {
1698 //
1699 // Read a word if StartAddress is word aligned
1700 //
1701 WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));
1702
1703 StartAddress += sizeof (UINT16);
1704 Size -= sizeof (UINT16);
1705 Buffer = (UINT16 *)Buffer + 1;
1706 }
1707
1708 while (Size >= sizeof (UINT32)) {
1709 //
1710 // Read as many double words as possible
1711 //
1712 WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciExpressRead32 (StartAddress));
1713
1714 StartAddress += sizeof (UINT32);
1715 Size -= sizeof (UINT32);
1716 Buffer = (UINT32 *)Buffer + 1;
1717 }
1718
1719 if (Size >= sizeof (UINT16)) {
1720 //
1721 // Read the last remaining word if exist
1722 //
1723 WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));
1724 StartAddress += sizeof (UINT16);
1725 Size -= sizeof (UINT16);
1726 Buffer = (UINT16 *)Buffer + 1;
1727 }
1728
1729 if (Size >= sizeof (UINT8)) {
1730 //
1731 // Read the last remaining byte if exist
1732 //
1733 *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
1734 }
1735
1736 return ReturnValue;
1737}
1738
1764UINTN
1765EFIAPI
1767 IN UINTN StartAddress,
1768 IN UINTN Size,
1769 IN VOID *Buffer
1770 )
1771{
1772 UINTN ReturnValue;
1773
1774 //
1775 // Make sure Address is valid
1776 //
1777 ASSERT_INVALID_PCI_ADDRESS (StartAddress);
1778 ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
1779
1780 //
1781 // Make sure the Address is in MMCONF address space
1782 //
1783 if (StartAddress >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
1784 return (UINTN)-1;
1785 }
1786
1787 if (Size == 0) {
1788 return 0;
1789 }
1790
1791 ASSERT (Buffer != NULL);
1792
1793 //
1794 // Save Size for return
1795 //
1796 ReturnValue = Size;
1797
1798 if ((StartAddress & 1) != 0) {
1799 //
1800 // Write a byte if StartAddress is byte aligned
1801 //
1802 PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);
1803 StartAddress += sizeof (UINT8);
1804 Size -= sizeof (UINT8);
1805 Buffer = (UINT8 *)Buffer + 1;
1806 }
1807
1808 if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {
1809 //
1810 // Write a word if StartAddress is word aligned
1811 //
1812 PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));
1813 StartAddress += sizeof (UINT16);
1814 Size -= sizeof (UINT16);
1815 Buffer = (UINT16 *)Buffer + 1;
1816 }
1817
1818 while (Size >= sizeof (UINT32)) {
1819 //
1820 // Write as many double words as possible
1821 //
1822 PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));
1823 StartAddress += sizeof (UINT32);
1824 Size -= sizeof (UINT32);
1825 Buffer = (UINT32 *)Buffer + 1;
1826 }
1827
1828 if (Size >= sizeof (UINT16)) {
1829 //
1830 // Write the last remaining word if exist
1831 //
1832 PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));
1833 StartAddress += sizeof (UINT16);
1834 Size -= sizeof (UINT16);
1835 Buffer = (UINT16 *)Buffer + 1;
1836 }
1837
1838 if (Size >= sizeof (UINT8)) {
1839 //
1840 // Write the last remaining byte if exist
1841 //
1842 PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);
1843 }
1844
1845 return ReturnValue;
1846}
UINT64 UINTN
UINT16 EFIAPI ReadUnaligned16(IN CONST UINT16 *Buffer)
Definition: Unaligned.c:29
UINT32 EFIAPI WriteUnaligned32(OUT UINT32 *Buffer, IN UINT32 Value)
Definition: Unaligned.c:177
VOID EFIAPI CpuBreakpoint(VOID)
Definition: CpuBreakpoint.c:26
UINT16 EFIAPI WriteUnaligned16(OUT UINT16 *Buffer, IN UINT16 Value)
Definition: Unaligned.c:61
UINT32 EFIAPI ReadUnaligned32(IN CONST UINT32 *Buffer)
Definition: Unaligned.c:145
EFI_DXE_SERVICES * gDS
VOID EFIAPI FreePool(IN VOID *Buffer)
VOID *EFIAPI ReallocateRuntimePool(IN UINTN OldSize, IN UINTN NewSize, IN VOID *OldBuffer OPTIONAL)
UINT16 EFIAPI MmioBitFieldAndThenOr16(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData, IN UINT16 OrData)
Definition: IoHighLevel.c:1750
UINT8 EFIAPI MmioBitFieldRead8(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)
Definition: IoHighLevel.c:1293
UINT32 EFIAPI MmioBitFieldWrite32(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 Value)
Definition: IoHighLevel.c:1912
UINT8 EFIAPI MmioBitFieldOr8(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 OrData)
Definition: IoHighLevel.c:1369
UINT8 EFIAPI MmioBitFieldWrite8(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 Value)
Definition: IoHighLevel.c:1327
UINT8 EFIAPI MmioAnd8(IN UINTN Address, IN UINT8 AndData)
Definition: IoHighLevel.c:1231
UINT16 EFIAPI MmioAndThenOr16(IN UINTN Address, IN UINT16 AndData, IN UINT16 OrData)
Definition: IoHighLevel.c:1551
UINT32 EFIAPI MmioBitFieldAndThenOr32(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData, IN UINT32 OrData)
Definition: IoHighLevel.c:2044
UINT8 EFIAPI MmioBitFieldAndThenOr8(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData, IN UINT8 OrData)
Definition: IoHighLevel.c:1456
UINT16 EFIAPI MmioBitFieldWrite16(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 Value)
Definition: IoHighLevel.c:1618
UINT32 EFIAPI MmioBitFieldOr32(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 OrData)
Definition: IoHighLevel.c:1955
UINT16 EFIAPI MmioBitFieldAnd16(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData)
Definition: IoHighLevel.c:1704
UINT32 EFIAPI MmioBitFieldRead32(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)
Definition: IoHighLevel.c:1877
UINT16 EFIAPI MmioBitFieldOr16(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 OrData)
Definition: IoHighLevel.c:1661
UINT32 EFIAPI MmioAnd32(IN UINTN Address, IN UINT32 AndData)
Definition: IoHighLevel.c:1814
UINT32 EFIAPI MmioOr32(IN UINTN Address, IN UINT32 OrData)
Definition: IoHighLevel.c:1785
UINT8 EFIAPI MmioAndThenOr8(IN UINTN Address, IN UINT8 AndData, IN UINT8 OrData)
Definition: IoHighLevel.c:1262
UINT16 EFIAPI MmioBitFieldRead16(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)
Definition: IoHighLevel.c:1583
UINT16 EFIAPI MmioRead16(IN UINTN Address)
Definition: IoLib.c:170
UINT8 EFIAPI MmioRead8(IN UINTN Address)
Definition: IoLib.c:82
UINT8 EFIAPI MmioOr8(IN UINTN Address, IN UINT8 OrData)
Definition: IoHighLevel.c:1203
UINT8 EFIAPI MmioWrite8(IN UINTN Address, IN UINT8 Value)
Definition: IoLib.c:126
UINT32 EFIAPI MmioRead32(IN UINTN Address)
Definition: IoLib.c:262
UINT16 EFIAPI MmioAnd16(IN UINTN Address, IN UINT16 AndData)
Definition: IoHighLevel.c:1520
UINT8 EFIAPI MmioBitFieldAnd8(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData)
Definition: IoHighLevel.c:1411
UINT16 EFIAPI MmioOr16(IN UINTN Address, IN UINT16 OrData)
Definition: IoHighLevel.c:1491
UINT16 EFIAPI MmioWrite16(IN UINTN Address, IN UINT16 Value)
Definition: IoLib.c:216
UINT32 EFIAPI MmioAndThenOr32(IN UINTN Address, IN UINT32 AndData, IN UINT32 OrData)
Definition: IoHighLevel.c:1845
UINT32 EFIAPI MmioBitFieldAnd32(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData)
Definition: IoHighLevel.c:1998
UINT32 EFIAPI MmioWrite32(IN UINTN Address, IN UINT32 Value)
Definition: IoLib.c:309
#define NULL
Definition: Base.h:319
#define RETURN_UNSUPPORTED
Definition: Base.h:1081
#define RETURN_OUT_OF_RESOURCES
Definition: Base.h:1114
#define RETURN_SUCCESS
Definition: Base.h:1066
#define IN
Definition: Base.h:279
#define OUT
Definition: Base.h:284
#define ASSERT_EFI_ERROR(StatusParameter)
Definition: DebugLib.h:462
RETURN_STATUS EFIAPI PciExpressRegisterForRuntimeAccess(IN UINTN Address)
Definition: PciExpressLib.c:56
UINT8 EFIAPI PciExpressBitFieldAnd8(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData)
UINT32 EFIAPI PciExpressWrite32(IN UINTN Address, IN UINT32 Value)
UINT16 EFIAPI PciExpressBitFieldAnd16(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData)
UINT8 EFIAPI PciExpressAndThenOr8(IN UINTN Address, IN UINT8 AndData, IN UINT8 OrData)
UINT32 EFIAPI PciExpressBitFieldOr32(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 OrData)
UINT16 EFIAPI PciExpressOr16(IN UINTN Address, IN UINT16 OrData)
UINT8 EFIAPI PciExpressBitFieldAndThenOr8(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 AndData, IN UINT8 OrData)
UINT16 EFIAPI PciExpressBitFieldAndThenOr16(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 AndData, IN UINT16 OrData)
UINT32 EFIAPI PciExpressBitFieldWrite32(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 Value)
UINT16 EFIAPI PciExpressRead16(IN UINTN Address)
UINTN EFIAPI PciExpressReadBuffer(IN UINTN StartAddress, IN UINTN Size, OUT VOID *Buffer)
UINT8 EFIAPI PciExpressWrite8(IN UINTN Address, IN UINT8 Value)
UINT8 EFIAPI PciExpressBitFieldWrite8(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 Value)
UINT8 EFIAPI PciExpressAnd8(IN UINTN Address, IN UINT8 AndData)
UINT32 EFIAPI PciExpressOr32(IN UINTN Address, IN UINT32 OrData)
UINT16 EFIAPI PciExpressWrite16(IN UINTN Address, IN UINT16 Value)
UINTN EFIAPI PciExpressWriteBuffer(IN UINTN StartAddress, IN UINTN Size, IN VOID *Buffer)
UINT8 EFIAPI PciExpressOr8(IN UINTN Address, IN UINT8 OrData)
#define ASSERT_INVALID_PCI_ADDRESS(A)
Definition: PciExpressLib.c:29
UINT32 EFIAPI PciExpressBitFieldAndThenOr32(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData, IN UINT32 OrData)
UINT8 EFIAPI PciExpressBitFieldOr8(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT8 OrData)
UINT32 EFIAPI PciExpressBitFieldAnd32(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT32 AndData)
UINT16 EFIAPI PciExpressBitFieldWrite16(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 Value)
UINT16 EFIAPI PciExpressBitFieldOr16(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit, IN UINT16 OrData)
UINT16 EFIAPI PciExpressAndThenOr16(IN UINTN Address, IN UINT16 AndData, IN UINT16 OrData)
UINT32 EFIAPI PciExpressAndThenOr32(IN UINTN Address, IN UINT32 AndData, IN UINT32 OrData)
UINT8 EFIAPI PciExpressBitFieldRead8(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)
UINT16 EFIAPI PciExpressAnd16(IN UINTN Address, IN UINT16 AndData)
UINT8 EFIAPI PciExpressRead8(IN UINTN Address)
UINT32 EFIAPI PciExpressBitFieldRead32(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)
UINT32 EFIAPI PciExpressAnd32(IN UINTN Address, IN UINT32 AndData)
UINT32 EFIAPI PciExpressRead32(IN UINTN Address)
STATIC UINTN PcdPciExpressBaseSize(VOID)
Definition: PciExpressLib.c:92
UINT16 EFIAPI PciExpressBitFieldRead16(IN UINTN Address, IN UINTN StartBit, IN UINTN EndBit)
UINTN mDxeRuntimePciExpressLibPciExpressBaseAddress
Definition: PciExpressLib.c:53
UINTN mDxeRuntimePciExpressLibNumberOfRuntimeRanges
Definition: PciExpressLib.c:59
UINTN mDxeRuntimePciExpressLibLastRuntimeRange
Definition: PciExpressLib.c:69
PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE * mDxeRuntimePciExpressLibRegistrationTable
Definition: PciExpressLib.c:64
EFI_EVENT mDxeRuntimePciExpressLibVirtualNotifyEvent
Definition: PciExpressLib.c:48
EFI_STATUS EFIAPI DxeRuntimePciExpressLibConstructor(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
VOID EFIAPI DxeRuntimePciExpressLibVirtualNotify(IN EFI_EVENT Event, IN VOID *Context)
Definition: PciExpressLib.c:80
UINTN GetPciExpressAddress(IN UINTN Address)
EFI_STATUS EFIAPI DxeRuntimePciExpressLibDestructor(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
#define PcdGet64(TokenName)
Definition: PcdLib.h:375
RETURN_STATUS EFI_STATUS
Definition: UefiBaseType.h:29
VOID * EFI_EVENT
Definition: UefiBaseType.h:37
VOID * EFI_HANDLE
Definition: UefiBaseType.h:33
EFI_BOOT_SERVICES * gBS
BOOLEAN EFIAPI EfiAtRuntime(VOID)
Definition: RuntimeLib.c:167
EFI_STATUS EFIAPI EfiConvertPointer(IN UINTN DebugDisposition, IN OUT VOID **Address)
Definition: RuntimeLib.c:561
BOOLEAN EFIAPI EfiGoneVirtual(VOID)
Definition: RuntimeLib.c:188