TianoCore EDK2 master
Loading...
Searching...
No Matches
PageTables.h
Go to the documentation of this file.
1
17#ifndef PAGE_TABLES_H_
18#define PAGE_TABLES_H_
19
20#define SYS_CODE64_SEL 0x38
21
22#pragma pack(1)
23
24typedef union {
25 struct {
26 UINT32 LimitLow : 16;
27 UINT32 BaseLow : 16;
28 UINT32 BaseMid : 8;
29 UINT32 Type : 4;
30 UINT32 System : 1;
31 UINT32 Dpl : 2;
32 UINT32 Present : 1;
33 UINT32 LimitHigh : 4;
34 UINT32 Software : 1;
35 UINT32 Reserved : 1;
36 UINT32 DefaultSize : 1;
37 UINT32 Granularity : 1;
38 UINT32 BaseHigh : 8;
39 } Bits;
40 UINT64 Uint64;
41} IA32_GDT;
42
43typedef struct {
44 IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry;
45 UINT32 Offset32To63;
46 UINT32 Reserved;
48
49//
50// Page-Map Level-4 Offset (PML4) and
51// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
52//
53
54typedef union {
55 struct {
56 UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
57 UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
58 UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
59 UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
60 UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
61 UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
62 UINT64 Reserved : 1; // Reserved
63 UINT64 MustBeZero : 2; // Must Be Zero
64 UINT64 Available : 3; // Available for use by system software
65 UINT64 PageTableBaseAddress : 40; // Page Table Base Address
66 UINT64 AvabilableHigh : 11; // Available for use by system software
67 UINT64 Nx : 1; // No Execute bit
68 } Bits;
69 UINT64 Uint64;
71
72//
73// Page Table Entry 4KB
74//
75typedef union {
76 struct {
77 UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
78 UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
79 UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
80 UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
81 UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
82 UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
83 UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page
84 UINT64 PAT : 1; //
85 UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
86 UINT64 Available : 3; // Available for use by system software
87 UINT64 PageTableBaseAddress : 40; // Page Table Base Address
88 UINT64 AvabilableHigh : 11; // Available for use by system software
89 UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution
90 } Bits;
91 UINT64 Uint64;
93
94//
95// Page Table Entry 2MB
96//
97typedef union {
98 struct {
99 UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
100 UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
101 UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
102 UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
103 UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
104 UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
105 UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page
106 UINT64 MustBe1 : 1; // Must be 1
107 UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
108 UINT64 Available : 3; // Available for use by system software
109 UINT64 PAT : 1; //
110 UINT64 MustBeZero : 8; // Must be zero;
111 UINT64 PageTableBaseAddress : 31; // Page Table Base Address
112 UINT64 AvabilableHigh : 11; // Available for use by system software
113 UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution
114 } Bits;
115 UINT64 Uint64;
117
118//
119// Page Table Entry 1GB
120//
121typedef union {
122 struct {
123 UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
124 UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
125 UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
126 UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
127 UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
128 UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
129 UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page
130 UINT64 MustBe1 : 1; // Must be 1
131 UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
132 UINT64 Available : 3; // Available for use by system software
133 UINT64 PAT : 1; //
134 UINT64 MustBeZero : 17; // Must be zero;
135 UINT64 PageTableBaseAddress : 22; // Page Table Base Address
136 UINT64 AvabilableHigh : 11; // Available for use by system software
137 UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution
138 } Bits;
139 UINT64 Uint64;
141
142#pragma pack()
143
144#define CR0_WP BIT16
145
146#define IA32_PG_P BIT0
147#define IA32_PG_RW BIT1
148#define IA32_PG_PS BIT7
149
150#define PAGING_PAE_INDEX_MASK 0x1FF
151
152#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
153#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
154#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
155
156#define PAGING_L1_ADDRESS_SHIFT 12
157#define PAGING_L2_ADDRESS_SHIFT 21
158#define PAGING_L3_ADDRESS_SHIFT 30
159#define PAGING_L4_ADDRESS_SHIFT 39
160
161#define PAGING_PML4E_NUMBER 4
162
163#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB
164#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB
165#define PAGE_TABLE_POOL_UNIT_PAGES EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)
166#define PAGE_TABLE_POOL_ALIGN_MASK \
167 (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))
168
169typedef struct {
170 VOID *NextPool;
171 UINTN Offset;
174
175UINTN
177 IN EFI_PHYSICAL_ADDRESS StackBase,
178 IN UINTN StackSize
179 );
180
190VOID
192 IN VOID *HobStart
193 );
194
201BOOLEAN
203 VOID
204 );
205
206#endif
UINT64 UINTN
VOID EFIAPI FreePages(IN VOID *Buffer, IN UINTN Pages)
#define IN
Definition: Base.h:279
UINTN CreateIdentityMappingPageTables(IN EFI_PHYSICAL_ADDRESS StackBase, IN UINTN StackSize)
VOID ClearFirst4KPage(IN VOID *HobStart)
Definition: VirtualMemory.c:44
BOOLEAN IsNullDetectionEnabled(VOID)
UINT64 EFI_PHYSICAL_ADDRESS
Definition: UefiBaseType.h:50