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#ifndef REGS_SPI_H_

#define REGS_SPI_H_


#define R_SPI_BASE                        0x10

#define B_SPI_BAR0_MASK                   0x0FFF

#define R_SPI_BCR                         0xDC

#define B_SPI_BCR_SRC                     (BIT3 | BIT2)

#define V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS  0x04

#define B_SPI_BCR_SYNC_SS                 BIT8

#define B_SPI_BCR_BIOSWE                  BIT0


#define R_SPI_HSFS                      0x04

#define B_SPI_HSFS_FDBC_MASK            0x3F000000

#define N_SPI_HSFS_FDBC                 24

#define B_SPI_HSFS_CYCLE_MASK           0x001E0000

#define N_SPI_HSFS_CYCLE                17

#define V_SPI_HSFS_CYCLE_READ           0

#define V_SPI_HSFS_CYCLE_WRITE          2

#define V_SPI_HSFS_CYCLE_4K_ERASE       3

#define V_SPI_HSFS_CYCLE_64K_ERASE      4

#define V_SPI_HSFS_CYCLE_READ_SFDP      5

#define V_SPI_HSFS_CYCLE_READ_JEDEC_ID  6

#define V_SPI_HSFS_CYCLE_WRITE_STATUS   7

#define V_SPI_HSFS_CYCLE_READ_STATUS    8

#define B_SPI_HSFS_CYCLE_FGO            BIT16

#define B_SPI_HSFS_FDV                  BIT14

#define B_SPI_HSFS_SCIP                 BIT5

#define B_SPI_HSFS_FCERR                BIT1

#define B_SPI_HSFS_FDONE                BIT0


#define R_SPI_FADDR       0x08

#define B_SPI_FADDR_MASK  0x07FFFFFF


#define R_SPI_FDATA00  0x10


#define R_SPI_FRAP                0x50

#define B_SPI_FRAP_BRWA_PLATFORM  BIT12        // < Region write access for Region4 PlatformData

#define B_SPI_FRAP_BRWA_GBE       BIT11        // < Region write access for Region3 GbE

#define B_SPI_FRAP_BRWA_SEC       BIT10

#define B_SPI_FRAP_BRWA_BIOS      BIT9

#define B_SPI_FRAP_BRWA_FLASHD    BIT8

#define B_SPI_FRAP_BRRA_PLATFORM  BIT4

#define B_SPI_FRAP_BRRA_GBE       BIT3

#define B_SPI_FRAP_BRRA_SEC       BIT2

#define B_SPI_FRAP_BRRA_BIOS      BIT1

#define B_SPI_FRAP_BRRA_FLASHD    BIT0


#define R_SPI_FREG0_FLASHD      0x54

#define B_SPI_FREG0_LIMIT_MASK  0x7FFF0000

#define N_SPI_FREG0_LIMIT       4

#define B_SPI_FREG0_BASE_MASK   0x00007FFF

#define N_SPI_FREG0_BASE        12


#define R_SPI_FREG1_BIOS        0x58

#define B_SPI_FREG1_LIMIT_MASK  0x7FFF0000

#define N_SPI_FREG1_LIMIT       4

#define B_SPI_FREG1_BASE_MASK   0x00007FFF

#define N_SPI_FREG1_BASE        12


#define R_SPI_FREG2_SEC         0x5C

#define B_SPI_FREG2_LIMIT_MASK  0x7FFF0000

#define N_SPI_FREG2_LIMIT       4                   // < Bit 30:16 identifies address bits [26:12]

#define B_SPI_FREG2_BASE_MASK   0x00007FFF

#define N_SPI_FREG2_BASE        12                  // < Bit 14:0 identifies address bits [26:2]


#define R_SPI_FREG3_GBE         0x60                // < Flash Region 3(GbE)(32bits)

#define B_SPI_FREG3_LIMIT_MASK  0x7FFF0000

#define N_SPI_FREG3_LIMIT       4                   // < Bit 30:16 identifies address bits [26:12]

#define B_SPI_FREG3_BASE_MASK   0x00007FFF

#define N_SPI_FREG3_BASE        12                  // < Bit 14:0 identifies address bits [26:2]


#define R_SPI_FREG4_PLATFORM_DATA  0x64

#define B_SPI_FREG4_LIMIT_MASK     0x7FFF0000

#define N_SPI_FREG4_LIMIT          4

#define B_SPI_FREG4_BASE_MASK      0x00007FFF

#define N_SPI_FREG4_BASE           12


#define S_SPI_FREGX             4

#define B_SPI_FREGX_LIMIT_MASK  0x7FFF0000

#define N_SPI_FREGX_LIMIT       16

#define N_SPI_FREGX_LIMIT_REPR  12

#define B_SPI_FREGX_BASE_MASK   0x00007FFF


#define R_SPI_FDOC            0xB4

#define B_SPI_FDOC_FDSS_MASK  (BIT14 | BIT13 | BIT12)

#define V_SPI_FDOC_FDSS_FSDM  0x0000

#define V_SPI_FDOC_FDSS_COMP  0x1000

#define B_SPI_FDOC_FDSI_MASK  0x0FFC


#define R_SPI_FDOD  0xB8


#define R_SPI_LVSCC         0xC4

#define B_SPI_LVSCC_EO_64K  BIT29


#define R_SPI_UVSCC  0xC8


#define R_SPI_FDBAR_FLASH_MAP0  0x14

#define N_SPI_FDBAR_NC          8

#define B_SPI_FDBAR_NC          0x00000300


#define R_SPI_FDBAR_FLASH_MAP1  0x18

#define B_SPI_FDBAR_FPSBA       0x00FF0000


//

// Flash Component Base Address (FCBA) from Flash Region 0

//

#define R_SPI_FCBA_FLCOMP        0x00

#define B_SPI_FLCOMP_COMP1_MASK  0x0F


#endif