CPUID_CACHE_INFO_CACHE_TLB Union Reference

#include <MdePkg/Include/Register/Intel/Cpuid.h>

Data Fields
struct {
UINT32   Reserved: 31
UINT32   NotValid: 1
}	Bits
UINT8	CacheDescriptor [4]
UINT32	Uint32

Detailed Description

CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID leaf CPUID_CACHE_INFO.

Definition at line 716 of file Cpuid.h.

Field Documentation

struct { ... } CPUID_CACHE_INFO_CACHE_TLB::Bits

Individual bit fields

CacheDescriptor

UINT8 CPUID_CACHE_INFO_CACHE_TLB::CacheDescriptor[4]

Array of Cache and TLB descriptor bytes

Definition at line 731 of file Cpuid.h.

NotValid

UINT32 CPUID_CACHE_INFO_CACHE_TLB::NotValid

[Bit 31] If 0, then the cache descriptor bytes in the register are valid. if 1, then none of the cache descriptor bytes in the register are valid.

Definition at line 726 of file Cpuid.h.

Reserved

UINT32 CPUID_CACHE_INFO_CACHE_TLB::Reserved

Definition at line 721 of file Cpuid.h.

Uint32

UINT32 CPUID_CACHE_INFO_CACHE_TLB::Uint32

All bit fields as a 32-bit value

Definition at line 735 of file Cpuid.h.

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The documentation for this union was generated from the following file:

• MdePkg/Include/Register/Intel/Cpuid.h