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TianoCore EDK2 master
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#include <MdePkg/Include/Register/Intel/ArchitecturalMsr.h>
Data Fields | |
| struct { | |
| UINT32 Minimum_Performance: 8 | |
| UINT32 Maximum_Performance: 8 | |
| UINT32 Desired_Performance: 8 | |
| UINT32 Energy_Performance_Preference: 8 | |
| UINT32 Activity_Window: 10 | |
| UINT32 Reserved: 22 | |
| } | Bits |
| UINT64 | Uint64 |
MSR information returned for MSR index MSR_IA32_HWP_REQUEST_PKG
Definition at line 5003 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Activity_Window |
[Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
Definition at line 5032 of file ArchitecturalMsr.h.
| struct { ... } MSR_IA32_HWP_REQUEST_PKG_REGISTER::Bits |
Individual bit fields
| UINT32 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Desired_Performance |
[Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[11] = 1.
Definition at line 5022 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Energy_Performance_Preference |
[Bits 31:24] Energy_Performance_Preference See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
Definition at line 5027 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Maximum_Performance |
[Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[11] = 1.
Definition at line 5017 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Minimum_Performance |
[Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[11] = 1.
Definition at line 5012 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Reserved |
Definition at line 5033 of file ArchitecturalMsr.h.
| UINT64 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Uint64 |
All bit fields as a 64-bit value
Definition at line 5038 of file ArchitecturalMsr.h.