|
TianoCore EDK2 master
|
#include <MdePkg/Include/Register/Intel/ArchitecturalMsr.h>
Data Fields | |
| struct { | |
| UINT32 Guaranteed_Performance_Change: 1 | |
| UINT32 Reserved1: 1 | |
| UINT32 Excursion_To_Minimum: 1 | |
| UINT32 Reserved2: 29 | |
| UINT32 Reserved3: 32 | |
| } | Bits |
| UINT32 | Uint32 |
| UINT64 | Uint64 |
MSR information returned for MSR index MSR_IA32_HWP_STATUS
Definition at line 5183 of file ArchitecturalMsr.h.
| struct { ... } MSR_IA32_HWP_STATUS_REGISTER::Bits |
Individual bit fields
| UINT32 MSR_IA32_HWP_STATUS_REGISTER::Excursion_To_Minimum |
[Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
Definition at line 5198 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_HWP_STATUS_REGISTER::Guaranteed_Performance_Change |
[Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5, "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
Definition at line 5192 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_HWP_STATUS_REGISTER::Reserved1 |
Definition at line 5193 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_HWP_STATUS_REGISTER::Reserved2 |
Definition at line 5199 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_HWP_STATUS_REGISTER::Reserved3 |
Definition at line 5200 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_HWP_STATUS_REGISTER::Uint32 |
All bit fields as a 32-bit value
Definition at line 5205 of file ArchitecturalMsr.h.
| UINT64 MSR_IA32_HWP_STATUS_REGISTER::Uint64 |
All bit fields as a 64-bit value
Definition at line 5209 of file ArchitecturalMsr.h.