MSR_IA32_L3_QOS_CFG_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/ArchitecturalMsr.h>

Data Fields
struct {
UINT32   Enable: 1
UINT32   Reserved1: 31
UINT32   Reserved2: 32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_IA32_L3_QOS_CFG

Definition at line 5873 of file ArchitecturalMsr.h.

Field Documentation

struct { ... } MSR_IA32_L3_QOS_CFG_REGISTER::Bits

Individual bit fields

Enable

UINT32 MSR_IA32_L3_QOS_CFG_REGISTER::Enable

[Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate in Code and Data Prioritization (CDP) mode.

Definition at line 5882 of file ArchitecturalMsr.h.

Reserved1

UINT32 MSR_IA32_L3_QOS_CFG_REGISTER::Reserved1

Definition at line 5883 of file ArchitecturalMsr.h.

Reserved2

UINT32 MSR_IA32_L3_QOS_CFG_REGISTER::Reserved2

Definition at line 5884 of file ArchitecturalMsr.h.

Uint32

UINT32 MSR_IA32_L3_QOS_CFG_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 5889 of file ArchitecturalMsr.h.

Uint64

UINT64 MSR_IA32_L3_QOS_CFG_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 5893 of file ArchitecturalMsr.h.

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The documentation for this union was generated from the following file:

• MdePkg/Include/Register/Intel/ArchitecturalMsr.h