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TianoCore EDK2 master
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#include <MdePkg/Include/Register/Intel/ArchitecturalMsr.h>
Data Fields | |
| struct { | |
| UINT32 LBR_FMT: 6 | |
| UINT32 PEBS_TRAP: 1 | |
| UINT32 PEBS_ARCH_REG: 1 | |
| UINT32 PEBS_REC_FMT: 4 | |
| UINT32 SMM_FREEZE: 1 | |
| UINT32 FW_WRITE: 1 | |
| UINT32 Reserved1: 18 | |
| UINT32 Reserved2: 32 | |
| } | Bits |
| UINT32 | Uint32 |
| UINT64 | Uint64 |
MSR information returned for MSR index MSR_IA32_PERF_CAPABILITIES
Definition at line 2745 of file ArchitecturalMsr.h.
| struct { ... } MSR_IA32_PERF_CAPABILITIES_REGISTER::Bits |
Individual bit fields
| UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::FW_WRITE |
[Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
Definition at line 2773 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::LBR_FMT |
[Bits 5:0] LBR format.
Definition at line 2753 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::PEBS_ARCH_REG |
[Bit 7] PEBSSaveArchRegs.
Definition at line 2761 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::PEBS_REC_FMT |
[Bits 11:8] PEBS Record Format.
Definition at line 2765 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::PEBS_TRAP |
[Bit 6] PEBS Trap.
Definition at line 2757 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::Reserved1 |
Definition at line 2774 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::Reserved2 |
Definition at line 2775 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::SMM_FREEZE |
[Bit 12] 1: Freeze while SMM is supported.
Definition at line 2769 of file ArchitecturalMsr.h.
| UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::Uint32 |
All bit fields as a 32-bit value
Definition at line 2780 of file ArchitecturalMsr.h.
| UINT64 MSR_IA32_PERF_CAPABILITIES_REGISTER::Uint64 |
All bit fields as a 64-bit value
Definition at line 2784 of file ArchitecturalMsr.h.