MSR_IA32_PM_ENABLE_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/ArchitecturalMsr.h>

Data Fields
struct {
UINT32   HWP_ENABLE: 1
UINT32   Reserved1: 31
UINT32   Reserved2: 32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_IA32_PM_ENABLE

Definition at line 4897 of file ArchitecturalMsr.h.

Field Documentation

struct { ... } MSR_IA32_PM_ENABLE_REGISTER::Bits

Individual bit fields

HWP_ENABLE

UINT32 MSR_IA32_PM_ENABLE_REGISTER::HWP_ENABLE

[Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If CPUID.06H:EAX.[7] = 1.

Definition at line 4906 of file ArchitecturalMsr.h.

Reserved1

UINT32 MSR_IA32_PM_ENABLE_REGISTER::Reserved1

Definition at line 4907 of file ArchitecturalMsr.h.

Reserved2

UINT32 MSR_IA32_PM_ENABLE_REGISTER::Reserved2

Definition at line 4908 of file ArchitecturalMsr.h.

Uint32

UINT32 MSR_IA32_PM_ENABLE_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 4913 of file ArchitecturalMsr.h.

Uint64

UINT64 MSR_IA32_PM_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 4917 of file ArchitecturalMsr.h.

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The documentation for this union was generated from the following file:

• MdePkg/Include/Register/Intel/ArchitecturalMsr.h