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TianoCore EDK2 master
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#include <MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h>
Data Fields | |
| struct { | |
| UINT32 PKG_TDP_LVL2: 15 | |
| UINT32 Reserved1: 1 | |
| UINT32 Config_TDP_LVL2_Ratio: 8 | |
| UINT32 Reserved2: 8 | |
| UINT32 PKG_MAX_PWR_LVL2: 15 | |
| UINT32 Reserved3: 1 | |
| UINT32 PKG_MIN_PWR_LVL2: 15 | |
| UINT32 Reserved4: 1 | |
| } | Bits |
| UINT64 | Uint64 |
MSR information returned for MSR index MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2
Definition at line 354 of file IvyBridgeMsr.h.
| struct { ... } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::Bits |
Individual bit fields
| UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::Config_TDP_LVL2_Ratio |
[Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used for this specific processor.
Definition at line 368 of file IvyBridgeMsr.h.
| UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::PKG_MAX_PWR_LVL2 |
[Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP Level 2.
Definition at line 374 of file IvyBridgeMsr.h.
| UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::PKG_MIN_PWR_LVL2 |
[Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP Level 2.
Definition at line 380 of file IvyBridgeMsr.h.
| UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::PKG_TDP_LVL2 |
[Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
Definition at line 362 of file IvyBridgeMsr.h.
| UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::Reserved1 |
Definition at line 363 of file IvyBridgeMsr.h.
| UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::Reserved2 |
Definition at line 369 of file IvyBridgeMsr.h.
| UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::Reserved3 |
Definition at line 375 of file IvyBridgeMsr.h.
| UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::Reserved4 |
Definition at line 381 of file IvyBridgeMsr.h.
| UINT64 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::Uint64 |
All bit fields as a 64-bit value
Definition at line 386 of file IvyBridgeMsr.h.