#include <MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h>

Data Fields
struct {
UINT32 Reserved1: 8

UINT32 MaximumNonTurboRatio: 8

UINT32 Reserved2: 7

UINT32 PPIN_CAP: 1

UINT32 Reserved3: 4

UINT32 RatioLimit: 1

UINT32 TDPLimit: 1

UINT32 TJOFFSET: 1

UINT32 Reserved4: 1

UINT32 Reserved5: 8

UINT32 MaximumEfficiencyRatio: 8

UINT32 Reserved6: 16

}	Bits

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_IVY_BRIDGE_PLATFORM_INFO_1

Definition at line 594 of file IvyBridgeMsr.h.

Field Documentation

◆

struct { ... } MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::Bits

Individual bit fields

◆ MaximumEfficiencyRatio

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::MaximumEfficiencyRatio

[Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the minimum ratio (maximum efficiency) that the processor can operates, in units of 100MHz.

Definition at line 643 of file IvyBridgeMsr.h.

◆ MaximumNonTurboRatio

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::MaximumNonTurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz.

Definition at line 605 of file IvyBridgeMsr.h.

◆ PPIN_CAP

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::PPIN_CAP

[Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that Protected Processor Inventory Number (PPIN) capability can be enabled for privileged system inventory agent to read PPIN from MSR_PPIN. When set to 0, PPIN capability is not supported. An attempt to access MSR_PPIN_CTL or MSR_PPIN will cause #GP.

Definition at line 614 of file IvyBridgeMsr.h.

◆ RatioLimit

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::RatioLimit

[Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limits for Turbo mode is enabled, and when set to 0, indicates Programmable Ratio Limits for Turbo mode is disabled.

Definition at line 622 of file IvyBridgeMsr.h.

◆ Reserved1

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::Reserved1

Definition at line 599 of file IvyBridgeMsr.h.

◆ Reserved2

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::Reserved2

Definition at line 606 of file IvyBridgeMsr.h.

◆ Reserved3

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::Reserved3

Definition at line 615 of file IvyBridgeMsr.h.

◆ Reserved4

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::Reserved4

Definition at line 636 of file IvyBridgeMsr.h.

◆ Reserved5

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::Reserved5

Definition at line 637 of file IvyBridgeMsr.h.

◆ Reserved6

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::Reserved6

Definition at line 644 of file IvyBridgeMsr.h.

◆ TDPLimit

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::TDPLimit

[Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limits for Turbo mode are programmable, and when set to 0, indicates TDP Limit for Turbo mode is not programmable.

Definition at line 629 of file IvyBridgeMsr.h.

◆ TJOFFSET

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::TJOFFSET

[Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1, indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to specify an temperature offset.

Definition at line 635 of file IvyBridgeMsr.h.

◆ Uint64

UINT64 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 649 of file IvyBridgeMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h

Data Fields