#include <MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h>

Data Fields
struct {
UINT32 Maximum9C: 8

UINT32 Maximum10C: 8

UINT32 Maximum11C: 8

UINT32 Maximum12C: 8

UINT32 Maximum13C: 8

UINT32 Maximum14C: 8

UINT32 Maximum15C: 8

UINT32 Reserved: 7

UINT32 TurboRatioLimitConfigurationSemaphore: 1

}	Bits

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1

Definition at line 776 of file IvyBridgeMsr.h.

Field Documentation

◆

struct { ... } MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Bits

Individual bit fields

◆ Maximum10C

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum10C

[Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio limit of 10core active.

Definition at line 790 of file IvyBridgeMsr.h.

◆ Maximum11C

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum11C

[Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio limit of 11 core active.

Definition at line 795 of file IvyBridgeMsr.h.

◆ Maximum12C

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum12C

[Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio limit of 12 core active.

Definition at line 800 of file IvyBridgeMsr.h.

◆ Maximum13C

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum13C

[Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio limit of 13 core active.

Definition at line 805 of file IvyBridgeMsr.h.

◆ Maximum14C

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum14C

[Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio limit of 14 core active.

Definition at line 810 of file IvyBridgeMsr.h.

◆ Maximum15C

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum15C

[Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio limit of 15 core active.

Definition at line 815 of file IvyBridgeMsr.h.

◆ Maximum9C

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum9C

[Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio limit of 9 core active.

Definition at line 785 of file IvyBridgeMsr.h.

◆ Reserved

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Reserved

Definition at line 816 of file IvyBridgeMsr.h.

◆ TurboRatioLimitConfigurationSemaphore

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::TurboRatioLimitConfigurationSemaphore

[Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1, the processor uses override configuration specified in MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor uses factory-set configuration (Default).

Definition at line 823 of file IvyBridgeMsr.h.

◆ Uint64

UINT64 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 828 of file IvyBridgeMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h

Data Fields