#include <MdePkg/Include/Register/Intel/Msr/Pentium4Msr.h>

Data Fields
struct {
UINT32 OutputTriStateEnabled: 1

UINT32 ExecuteBIST: 1

UINT32 InOrderQueueDepth: 1

UINT32 MCERR_ObservationDisabled: 1

UINT32 BINIT_ObservationEnabled: 1

UINT32 APICClusterID: 2

UINT32 BusParkDisable: 1

UINT32 Reserved1: 4

UINT32 AgentID: 2

UINT32 Reserved2: 18

UINT32 Reserved3: 32

}	Bits

UINT32	Uint32

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_PENTIUM_4_EBC_HARD_POWERON

Definition at line 80 of file Pentium4Msr.h.

Field Documentation

◆ AgentID

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::AgentID

[Bits 13:12] Agent ID (R) Contains the logical agent ID value as set by the strapping of BR[3:0]. The logical ID value is written into the field on the deassertion of RESET#; the field is set to 1 when the address bus signal is asserted.

Definition at line 141 of file Pentium4Msr.h.

◆ APICClusterID

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::APICClusterID

[Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID value as set by the strapping of A12# and A11#. The logical cluster ID value is written into the field on the deassertion of RESET#; the field is set to 1 when the address bus signal is asserted.

Definition at line 126 of file Pentium4Msr.h.

◆ BINIT_ObservationEnabled

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::BINIT_ObservationEnabled

[Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT# observation is enabled (0) or disabled (1) as determined by the strapping of A10#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.

Definition at line 119 of file Pentium4Msr.h.

◆

struct { ... } MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::Bits

Individual bit fields

◆ BusParkDisable

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::BusParkDisable

[Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled (0) or disabled (1) as set by the strapping of A15#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.

Definition at line 133 of file Pentium4Msr.h.

◆ ExecuteBIST

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::ExecuteBIST

[Bit 1] Execute BIST (R) Indicates whether the execution of the BIST is enabled (1) or disabled (0) as set by the strapping of INIT#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.

Definition at line 98 of file Pentium4Msr.h.

◆ InOrderQueueDepth

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::InOrderQueueDepth

[Bit 2] In Order Queue Depth (R) Indicates whether the in order queue depth for the system bus is 1 (1) or up to 12 (0) as set by the strapping of A7#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.

Definition at line 105 of file Pentium4Msr.h.

◆ MCERR_ObservationDisabled

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::MCERR_ObservationDisabled

[Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR# observation is enabled (0) or disabled (1) as determined by the strapping of A9#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.

Definition at line 112 of file Pentium4Msr.h.

◆ OutputTriStateEnabled

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::OutputTriStateEnabled

[Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state output is enabled (1) or disabled (0) as set by the strapping of SMI#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.

Definition at line 91 of file Pentium4Msr.h.

◆ Reserved1

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::Reserved1

Definition at line 134 of file Pentium4Msr.h.

◆ Reserved2

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::Reserved2

Definition at line 142 of file Pentium4Msr.h.

◆ Reserved3

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::Reserved3

Definition at line 143 of file Pentium4Msr.h.

◆ Uint32

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 148 of file Pentium4Msr.h.

◆ Uint64

UINT64 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 152 of file Pentium4Msr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/Pentium4Msr.h

Data Fields