#include <MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h>

Data Fields
struct {
UINT32 L2HardwareEnabled: 1

UINT32 Reserved1: 4

UINT32 ECCCheckEnable: 1

UINT32 Reserved2: 2

UINT32 L2Enabled: 1

UINT32 Reserved3: 14

UINT32 L2NotPresent: 1

UINT32 Reserved4: 8

UINT32 Reserved5: 32

}	Bits

UINT32	Uint32

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_PENTIUM_M_BBL_CR_CTL3

Definition at line 269 of file PentiumMMsr.h.

Field Documentation

◆

struct { ... } MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::Bits

Individual bit fields

◆ ECCCheckEnable

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::ECCCheckEnable

[Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the cache data bus. ECC is always generated on write cycles. 1. = Disabled (default) 2. = Enabled For the Pentium M processor, ECC checking on the cache data bus is always enabled.

Definition at line 286 of file PentiumMMsr.h.

◆ L2Enabled

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::L2Enabled

[Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 = Disabled (default) Until this bit is set the processor will not respond to the WBINVD instruction or the assertion of the FLUSH# input.

Definition at line 293 of file PentiumMMsr.h.

◆ L2HardwareEnabled

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::L2HardwareEnabled

[Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = Indicates if the L2 is hardware-disabled.

Definition at line 278 of file PentiumMMsr.h.

◆ L2NotPresent

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::L2NotPresent

[Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.

Definition at line 298 of file PentiumMMsr.h.

◆ Reserved1

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::Reserved1

Definition at line 279 of file PentiumMMsr.h.

◆ Reserved2

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::Reserved2

Definition at line 287 of file PentiumMMsr.h.

◆ Reserved3

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::Reserved3

Definition at line 294 of file PentiumMMsr.h.

◆ Reserved4

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::Reserved4

Definition at line 299 of file PentiumMMsr.h.

◆ Reserved5

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::Reserved5

Definition at line 300 of file PentiumMMsr.h.

◆ Uint32

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 305 of file PentiumMMsr.h.

◆ Uint64

UINT64 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 309 of file PentiumMMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h

Data Fields