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MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h>

Data Fields

struct {
   UINT32   Reserved1: 3
 
   UINT32   AutomaticThermalControlCircuit: 1
 
   UINT32   Reserved2: 3
 
   UINT32   PerformanceMonitoring: 1
 
   UINT32   Reserved3: 2
 
   UINT32   FERR: 1
 
   UINT32   BTS: 1
 
   UINT32   PEBS: 1
 
   UINT32   Reserved5: 3
 
   UINT32   EIST: 1
 
   UINT32   Reserved6: 6
 
   UINT32   xTPR_Message_Disable: 1
 
   UINT32   Reserved7: 8
 
   UINT32   Reserved8: 32
 
Bits
 
UINT32 Uint32
 
UINT64 Uint64
 

Detailed Description

MSR information returned for MSR index MSR_PENTIUM_M_IA32_MISC_ENABLE

Definition at line 386 of file PentiumMMsr.h.

Field Documentation

◆ AutomaticThermalControlCircuit

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting this bit enables the thermal control circuit (TCC) portion of the Intel Thermal Monitor feature. This allows processor clocks to be automatically modulated based on the processor's thermal sensor operation. 0 = Disabled (default). The automatic thermal control circuit enable bit determines if the thermal control circuit (TCC) will be activated when the processor's internal thermal sensor determines the processor is about to exceed its maximum operating temperature. When the TCC is activated and TM1 is enabled, the processors clocks will be forced to a 50% duty cycle. BIOS must enable this feature. The bit should not be confused with the on-demand thermal control circuit enable bit.

Definition at line 406 of file PentiumMMsr.h.

◆ 

struct { ... } MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

◆ BTS

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't support branch trace storage (BTS) 0 = BTS is supported

Definition at line 428 of file PentiumMMsr.h.

◆ EIST

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 = Enhanced Intel SpeedStep Technology enabled. On the Pentium M processor, this bit may be configured to be read-only.

Definition at line 441 of file PentiumMMsr.h.

◆ FERR

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::FERR

[Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the processor to indicate a pending break event within the processor 0 = Indicates compatible FERR# signaling behavior This bit must be set to 1 to support XAPIC interrupt model usage. Branch Trace Storage Unavailable (RO) 1 = Processor doesn't support branch trace storage (BTS) 0 = BTS is supported

Definition at line 422 of file PentiumMMsr.h.

◆ PEBS

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Processor Event Based Sampling Unavailable (RO) 1 = Processor does not support processor event based sampling (PEBS); 0 = PEBS is supported. The Pentium M processor does not support PEBS.

Definition at line 434 of file PentiumMMsr.h.

◆ PerformanceMonitoring

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Performance Monitoring Available (R) 1 = Performance monitoring enabled 0 = Performance monitoring disabled.

Definition at line 412 of file PentiumMMsr.h.

◆ Reserved1

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved1

Definition at line 391 of file PentiumMMsr.h.

◆ Reserved2

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved2

Definition at line 407 of file PentiumMMsr.h.

◆ Reserved3

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved3

Definition at line 413 of file PentiumMMsr.h.

◆ Reserved5

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved5

Definition at line 435 of file PentiumMMsr.h.

◆ Reserved6

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved6

Definition at line 442 of file PentiumMMsr.h.

◆ Reserved7

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved7

Definition at line 450 of file PentiumMMsr.h.

◆ Reserved8

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Reserved8

Definition at line 451 of file PentiumMMsr.h.

◆ Uint32

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 456 of file PentiumMMsr.h.

◆ Uint64

UINT64 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 460 of file PentiumMMsr.h.

◆ xTPR_Message_Disable

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are disabled. xTPR messages are optional messages that allow the processor to inform the chipset of its priority. The default is processor specific.

Definition at line 449 of file PentiumMMsr.h.


The documentation for this union was generated from the following file: