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Data Fields
MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h>

Data Fields

struct {
   UINT32   FastStrings: 1
 
   UINT32   Reserved1: 6
 
   UINT32   PerformanceMonitoring: 1
 
   UINT32   Reserved2: 3
 
   UINT32   BTS: 1
 
   UINT32   PEBS: 1
 
   UINT32   Reserved3: 3
 
   UINT32   EIST: 1
 
   UINT32   Reserved4: 1
 
   UINT32   MONITOR: 1
 
   UINT32   Reserved5: 3
 
   UINT32   LimitCpuidMaxval: 1
 
   UINT32   xTPR_Message_Disable: 1
 
   UINT32   Reserved6: 8
 
   UINT32   Reserved7: 2
 
   UINT32   XD: 1
 
   UINT32   Reserved8: 3
 
   UINT32   TurboModeDisable: 1
 
   UINT32   Reserved9: 25
 
} Bits
 
UINT64 Uint64
 

Detailed Description

MSR information returned for MSR index MSR_SANDY_BRIDGE_IA32_MISC_ENABLE

Definition at line 495 of file SandyBridgeMsr.h.

Field Documentation

◆ 

struct { ... } MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

◆ BTS

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.

Definition at line 513 of file SandyBridgeMsr.h.

◆ EIST

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2.

Definition at line 524 of file SandyBridgeMsr.h.

◆ FastStrings

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Thread. Fast-Strings Enable See Table 2-2.

Definition at line 503 of file SandyBridgeMsr.h.

◆ LimitCpuidMaxval

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.

Definition at line 534 of file SandyBridgeMsr.h.

◆ MONITOR

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.

Definition at line 529 of file SandyBridgeMsr.h.

◆ PEBS

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See Table 2-2.

Definition at line 518 of file SandyBridgeMsr.h.

◆ PerformanceMonitoring

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.

Definition at line 508 of file SandyBridgeMsr.h.

◆ Reserved1

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Reserved1

Definition at line 504 of file SandyBridgeMsr.h.

◆ Reserved2

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Reserved2

Definition at line 509 of file SandyBridgeMsr.h.

◆ Reserved3

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Reserved3

Definition at line 519 of file SandyBridgeMsr.h.

◆ Reserved4

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Reserved4

Definition at line 525 of file SandyBridgeMsr.h.

◆ Reserved5

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Reserved5

Definition at line 530 of file SandyBridgeMsr.h.

◆ Reserved6

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Reserved6

Definition at line 539 of file SandyBridgeMsr.h.

◆ Reserved7

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Reserved7

Definition at line 540 of file SandyBridgeMsr.h.

◆ Reserved8

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Reserved8

Definition at line 545 of file SandyBridgeMsr.h.

◆ Reserved9

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Reserved9

Definition at line 558 of file SandyBridgeMsr.h.

◆ TurboModeDisable

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::TurboModeDisable

[Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors that support Intel Turbo Boost Technology, the turbo mode feature is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor's support of turbo mode is enabled. Note: the power-on default value is used by BIOS to detect hardware support of turbo mode. If power-on default value is 1, turbo mode is available in the processor. If power-on default value is 0, turbo mode is not available.

Definition at line 557 of file SandyBridgeMsr.h.

◆ Uint64

UINT64 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 563 of file SandyBridgeMsr.h.

◆ XD

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.

Definition at line 544 of file SandyBridgeMsr.h.

◆ xTPR_Message_Disable

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.

Definition at line 538 of file SandyBridgeMsr.h.

The documentation for this union was generated from the following file: