#include <MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h>

Data Fields
struct {
UINT32 PCM0_EN: 1

UINT32 PCM1_EN: 1

UINT32 PCM2_EN: 1

UINT32 PCM3_EN: 1

UINT32 PCM4_EN: 1

UINT32 PCM5_EN: 1

UINT32 PCM6_EN: 1

UINT32 PCM7_EN: 1

UINT32 Reserved1: 24

UINT32 FIXED_CTR0: 1

UINT32 FIXED_CTR1: 1

UINT32 FIXED_CTR2: 1

UINT32 Reserved2: 29

}	Bits

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL

Definition at line 1025 of file SandyBridgeMsr.h.

Field Documentation

◆

struct { ... } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::Bits

Individual bit fields

◆ FIXED_CTR0

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::FIXED_CTR0

[Bit 32] Thread. Set 1 to enable FixedCtr0 to count.

Definition at line 1070 of file SandyBridgeMsr.h.

◆ FIXED_CTR1

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::FIXED_CTR1

[Bit 33] Thread. Set 1 to enable FixedCtr1 to count.

Definition at line 1074 of file SandyBridgeMsr.h.

◆ FIXED_CTR2

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::FIXED_CTR2

[Bit 34] Thread. Set 1 to enable FixedCtr2 to count.

Definition at line 1078 of file SandyBridgeMsr.h.

◆ PCM0_EN

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM0_EN

[Bit 0] Thread. Set 1 to enable PMC0 to count.

Definition at line 1033 of file SandyBridgeMsr.h.

◆ PCM1_EN

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM1_EN

[Bit 1] Thread. Set 1 to enable PMC1 to count.

Definition at line 1037 of file SandyBridgeMsr.h.

◆ PCM2_EN

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM2_EN

[Bit 2] Thread. Set 1 to enable PMC2 to count.

Definition at line 1041 of file SandyBridgeMsr.h.

◆ PCM3_EN

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM3_EN

[Bit 3] Thread. Set 1 to enable PMC3 to count.

Definition at line 1045 of file SandyBridgeMsr.h.

◆ PCM4_EN

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM4_EN

[Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] > 4).

Definition at line 1050 of file SandyBridgeMsr.h.

◆ PCM5_EN

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM5_EN

[Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] > 5).

Definition at line 1055 of file SandyBridgeMsr.h.

◆ PCM6_EN

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM6_EN

[Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] > 6).

Definition at line 1060 of file SandyBridgeMsr.h.

◆ PCM7_EN

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM7_EN

[Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] > 7).

Definition at line 1065 of file SandyBridgeMsr.h.

◆ Reserved1

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::Reserved1

Definition at line 1066 of file SandyBridgeMsr.h.

◆ Reserved2

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::Reserved2

Definition at line 1079 of file SandyBridgeMsr.h.

◆ Uint64

UINT64 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 1084 of file SandyBridgeMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h

Data Fields