#include <MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h>

Data Fields
struct {
UINT32 L2HardwarePrefetcherDisable: 1

UINT32 L2AdjacentCacheLinePrefetcherDisable: 1

UINT32 DCUHardwarePrefetcherDisable: 1

UINT32 DCUIPPrefetcherDisable: 1

UINT32 Reserved1: 28

UINT32 Reserved2: 32

}	Bits

UINT32	Uint32

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL

Definition at line 636 of file SandyBridgeMsr.h.

Field Documentation

◆

struct { ... } MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

◆ DCUHardwarePrefetcherDisable

UINT32 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::DCUHardwarePrefetcherDisable

[Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher, which fetches the next cache line into L1 data cache.

Definition at line 658 of file SandyBridgeMsr.h.

◆ DCUIPPrefetcherDisable

UINT32 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::DCUIPPrefetcherDisable

[Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1 data cache IP prefetcher, which uses sequential load history (based on instruction Pointer of previous loads) to determine whether to prefetch additional lines.

Definition at line 665 of file SandyBridgeMsr.h.

◆ L2AdjacentCacheLinePrefetcherDisable

UINT32 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::L2AdjacentCacheLinePrefetcherDisable

[Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1, disables the adjacent cache line prefetcher, which fetches the cache line that comprises a cache line pair (128 bytes).

Definition at line 652 of file SandyBridgeMsr.h.

◆ L2HardwarePrefetcherDisable

UINT32 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::L2HardwarePrefetcherDisable

[Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher, which fetches additional lines of code or data into the L2 cache.

Definition at line 646 of file SandyBridgeMsr.h.

◆ Reserved1

UINT32 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::Reserved1

Definition at line 666 of file SandyBridgeMsr.h.

◆ Reserved2

UINT32 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::Reserved2

Definition at line 667 of file SandyBridgeMsr.h.

◆ Uint32

UINT32 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 672 of file SandyBridgeMsr.h.

◆ Uint64

UINT64 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 676 of file SandyBridgeMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h

Data Fields