#include <MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h>

Data Fields
struct {
UINT32 PEBS_EN_PMC0: 1

UINT32 PEBS_EN_PMC1: 1

UINT32 PEBS_EN_PMC2: 1

UINT32 PEBS_EN_PMC3: 1

UINT32 Reserved1: 28

UINT32 LL_EN_PMC0: 1

UINT32 LL_EN_PMC1: 1

UINT32 LL_EN_PMC2: 1

UINT32 LL_EN_PMC3: 1

UINT32 Reserved2: 27

UINT32 PS_EN: 1

}	Bits

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SANDY_BRIDGE_PEBS_ENABLE

Definition at line 1204 of file SandyBridgeMsr.h.

Field Documentation

◆

struct { ... } MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

◆ LL_EN_PMC0

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::LL_EN_PMC0

[Bit 32] Enable Load Latency on IA32_PMC0. (R/W).

Definition at line 1229 of file SandyBridgeMsr.h.

◆ LL_EN_PMC1

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::LL_EN_PMC1

[Bit 33] Enable Load Latency on IA32_PMC1. (R/W).

Definition at line 1233 of file SandyBridgeMsr.h.

◆ LL_EN_PMC2

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::LL_EN_PMC2

[Bit 34] Enable Load Latency on IA32_PMC2. (R/W).

Definition at line 1237 of file SandyBridgeMsr.h.

◆ LL_EN_PMC3

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::LL_EN_PMC3

[Bit 35] Enable Load Latency on IA32_PMC3. (R/W).

Definition at line 1241 of file SandyBridgeMsr.h.

◆ PEBS_EN_PMC0

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::PEBS_EN_PMC0

[Bit 0] Enable PEBS on IA32_PMC0. (R/W).

Definition at line 1212 of file SandyBridgeMsr.h.

◆ PEBS_EN_PMC1

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::PEBS_EN_PMC1

[Bit 1] Enable PEBS on IA32_PMC1. (R/W).

Definition at line 1216 of file SandyBridgeMsr.h.

◆ PEBS_EN_PMC2

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::PEBS_EN_PMC2

[Bit 2] Enable PEBS on IA32_PMC2. (R/W).

Definition at line 1220 of file SandyBridgeMsr.h.

◆ PEBS_EN_PMC3

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::PEBS_EN_PMC3

[Bit 3] Enable PEBS on IA32_PMC3. (R/W).

Definition at line 1224 of file SandyBridgeMsr.h.

◆ PS_EN

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::PS_EN

[Bit 63] Enable Precise Store. (R/W).

Definition at line 1246 of file SandyBridgeMsr.h.

◆ Reserved1

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::Reserved1

Definition at line 1225 of file SandyBridgeMsr.h.

◆ Reserved2

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::Reserved2

Definition at line 1242 of file SandyBridgeMsr.h.

◆ Uint64

UINT64 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 1251 of file SandyBridgeMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h

Data Fields