#include <MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h>

Data Fields
struct {
UINT32 ScalableBusSpeed: 4

UINT32 Reserved1: 28

UINT32 Reserved2: 32

}	Bits

UINT32	Uint32

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SILVERMONT_FSB_FREQ

Definition at line 323 of file SilvermontMsr.h.

Field Documentation

◆

struct { ... } MSR_SILVERMONT_FSB_FREQ_REGISTER::Bits

Individual bit fields

◆ Reserved1

UINT32 MSR_SILVERMONT_FSB_FREQ_REGISTER::Reserved1

Definition at line 352 of file SilvermontMsr.h.

◆ Reserved2

UINT32 MSR_SILVERMONT_FSB_FREQ_REGISTER::Reserved2

Definition at line 353 of file SilvermontMsr.h.

◆ ScalableBusSpeed

UINT32 MSR_SILVERMONT_FSB_FREQ_REGISTER::ScalableBusSpeed

[Bits 3:0] Scalable Bus Speed

Silvermont Processor Family

100B: 080.0 MHz 000B: 083.3 MHz 001B: 100.0 MHz 010B: 133.3 MHz 011B: 116.7 MHz

Airmont Processor Family

0000B: 083.3 MHz 0001B: 100.0 MHz 0010B: 133.3 MHz 0011B: 116.7 MHz 0100B: 080.0 MHz 0101B: 093.3 MHz 0110B: 090.0 MHz 0111B: 088.9 MHz 1000B: 087.5 MHz

Definition at line 351 of file SilvermontMsr.h.

◆ Uint32

UINT32 MSR_SILVERMONT_FSB_FREQ_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 358 of file SilvermontMsr.h.

◆ Uint64

UINT64 MSR_SILVERMONT_FSB_FREQ_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 362 of file SilvermontMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h

Data Fields