#include <MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h>

Data Fields
struct {
UINT32 FastStrings: 1

UINT32 Reserved1: 2

UINT32 AutomaticThermalControlCircuit: 1

UINT32 Reserved2: 3

UINT32 PerformanceMonitoring: 1

UINT32 Reserved3: 3

UINT32 BTS: 1

UINT32 PEBS: 1

UINT32 Reserved4: 3

UINT32 EIST: 1

UINT32 Reserved5: 1

UINT32 MONITOR: 1

UINT32 Reserved6: 3

UINT32 LimitCpuidMaxval: 1

UINT32 xTPR_Message_Disable: 1

UINT32 Reserved7: 8

UINT32 Reserved8: 2

UINT32 XD: 1

UINT32 Reserved9: 3

UINT32 TurboModeDisable: 1

UINT32 Reserved10: 25

}	Bits

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SILVERMONT_IA32_MISC_ENABLE

Definition at line 671 of file SilvermontMsr.h.

Field Documentation

◆ AutomaticThermalControlCircuit

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See Table 2-2. Default value is 0.

Definition at line 685 of file SilvermontMsr.h.

◆

struct { ... } MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

◆ BTS

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.

Definition at line 695 of file SilvermontMsr.h.

◆ EIST

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2.

Definition at line 706 of file SilvermontMsr.h.

◆ FastStrings

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Core. Fast-Strings Enable See Table 2-2.

Definition at line 679 of file SilvermontMsr.h.

◆ LimitCpuidMaxval

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.

Definition at line 716 of file SilvermontMsr.h.

◆ MONITOR

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.

Definition at line 711 of file SilvermontMsr.h.

◆ PEBS

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See Table 2-2.

Definition at line 700 of file SilvermontMsr.h.

◆ PerformanceMonitoring

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.

Definition at line 690 of file SilvermontMsr.h.

◆ Reserved1

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Reserved1

Definition at line 680 of file SilvermontMsr.h.

◆ Reserved10

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Reserved10

Definition at line 740 of file SilvermontMsr.h.

◆ Reserved2

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Reserved2

Definition at line 686 of file SilvermontMsr.h.

◆ Reserved3

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Reserved3

Definition at line 691 of file SilvermontMsr.h.

◆ Reserved4

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Reserved4

Definition at line 701 of file SilvermontMsr.h.

◆ Reserved5

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Reserved5

Definition at line 707 of file SilvermontMsr.h.

◆ Reserved6

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Reserved6

Definition at line 712 of file SilvermontMsr.h.

◆ Reserved7

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Reserved7

Definition at line 721 of file SilvermontMsr.h.

◆ Reserved8

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Reserved8

Definition at line 722 of file SilvermontMsr.h.

◆ Reserved9

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Reserved9

Definition at line 727 of file SilvermontMsr.h.

◆ TurboModeDisable

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::TurboModeDisable

[Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors that support Intel Turbo Boost Technology, the turbo mode feature is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor's support of turbo mode is enabled. Note: the power-on default value is used by BIOS to detect hardware support of turbo mode. If power-on default value is 1, turbo mode is available in the processor. If power-on default value is 0, turbo mode is not available.

Definition at line 739 of file SilvermontMsr.h.

◆ Uint64

UINT64 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 745 of file SilvermontMsr.h.

◆ XD

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.

Definition at line 726 of file SilvermontMsr.h.

◆ xTPR_Message_Disable

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.

Definition at line 720 of file SilvermontMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h

Data Fields