#include <MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h>

Data Fields
struct {
UINT32 L2HardwarePrefetcherDisable: 1

UINT32 Reserved1: 1

UINT32 DCUHardwarePrefetcherDisable: 1

UINT32 Reserved2: 29

UINT32 Reserved3: 32

}	Bits

UINT32	Uint32

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SILVERMONT_MISC_FEATURE_CONTROL

Definition at line 826 of file SilvermontMsr.h.

Field Documentation

◆

struct { ... } MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

◆ DCUHardwarePrefetcherDisable

UINT32 MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::DCUHardwarePrefetcherDisable

[Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher, which fetches the next cache line into L1 data cache.

Definition at line 843 of file SilvermontMsr.h.

◆ L2HardwarePrefetcherDisable

UINT32 MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::L2HardwarePrefetcherDisable

[Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher, which fetches additional lines of code or data into the L2 cache.

Definition at line 836 of file SilvermontMsr.h.

◆ Reserved1

UINT32 MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::Reserved1

Definition at line 837 of file SilvermontMsr.h.

◆ Reserved2

UINT32 MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::Reserved2

Definition at line 844 of file SilvermontMsr.h.

◆ Reserved3

UINT32 MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::Reserved3

Definition at line 845 of file SilvermontMsr.h.

◆ Uint32

UINT32 MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 850 of file SilvermontMsr.h.

◆ Uint64

UINT64 MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 854 of file SilvermontMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h

Data Fields