MSR_SILVERMONT_PEBS_ENABLE_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h>

Data Fields
struct {
UINT32   PEBS: 1
UINT32   Reserved1: 31
UINT32   Reserved2: 32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SILVERMONT_PEBS_ENABLE

Definition at line 1129 of file SilvermontMsr.h.

Field Documentation

struct { ... } MSR_SILVERMONT_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

PEBS

UINT32 MSR_SILVERMONT_PEBS_ENABLE_REGISTER::PEBS

[Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).

Definition at line 1137 of file SilvermontMsr.h.

Reserved1

UINT32 MSR_SILVERMONT_PEBS_ENABLE_REGISTER::Reserved1

Definition at line 1138 of file SilvermontMsr.h.

Reserved2

UINT32 MSR_SILVERMONT_PEBS_ENABLE_REGISTER::Reserved2

Definition at line 1139 of file SilvermontMsr.h.

Uint32

UINT32 MSR_SILVERMONT_PEBS_ENABLE_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 1144 of file SilvermontMsr.h.

Uint64

UINT64 MSR_SILVERMONT_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 1148 of file SilvermontMsr.h.

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The documentation for this union was generated from the following file:

• MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h