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TianoCore EDK2 master
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#include <MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h>
Data Fields | |
| struct { | |
| UINT32 Limit: 15 | |
| UINT32 Enable: 1 | |
| UINT32 ClampingLimit: 1 | |
| UINT32 Time: 7 | |
| UINT32 Reserved1: 8 | |
| UINT32 Reserved2: 32 | |
| } | Bits |
| UINT32 | Uint32 |
| UINT64 | Uint64 |
MSR information returned for MSR index MSR_SILVERMONT_PKG_POWER_LIMIT
Definition at line 1334 of file SilvermontMsr.h.
| struct { ... } MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Bits |
Individual bit fields
| UINT32 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::ClampingLimit |
[Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3, "Package RAPL Domain.".
Definition at line 1353 of file SilvermontMsr.h.
| UINT32 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Enable |
[Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package RAPL Domain.".
Definition at line 1348 of file SilvermontMsr.h.
| UINT32 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Limit |
[Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.
Definition at line 1343 of file SilvermontMsr.h.
| UINT32 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Reserved1 |
Definition at line 1359 of file SilvermontMsr.h.
| UINT32 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Reserved2 |
Definition at line 1360 of file SilvermontMsr.h.
| UINT32 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Time |
[Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second. If 0 is specified in bits [23:17], defaults to 1 second window.
Definition at line 1358 of file SilvermontMsr.h.
| UINT32 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Uint32 |
All bit fields as a 32-bit value
Definition at line 1365 of file SilvermontMsr.h.
| UINT64 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Uint64 |
All bit fields as a 64-bit value
Definition at line 1369 of file SilvermontMsr.h.