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TianoCore EDK2 master
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#include <MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h>
Data Fields | |
| struct { | |
| UINT32 Lvl2Base: 16 | |
| UINT32 CStateRange: 3 | |
| UINT32 Reserved1: 13 | |
| UINT32 Reserved2: 32 | |
| } | Bits |
| UINT32 | Uint32 |
| UINT64 | Uint64 |
MSR information returned for MSR index MSR_SILVERMONT_PMG_IO_CAPTURE_BASE
Definition at line 502 of file SilvermontMsr.h.
| struct { ... } MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER::Bits |
Individual bit fields
| UINT32 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER::CStateRange |
[Bits 18:16] C-state Range (R/W) Specifies the encoding value of the maximum C-State code name to be included when IO read to MWAIT redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4 is the max C-State to include 110b - C6 is the max C-State to include 111b - C7 is the max C-State to include.
Definition at line 523 of file SilvermontMsr.h.
| UINT32 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER::Lvl2Base |
[Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address visible to software for IO redirection. If IO MWAIT Redirection is enabled, reads to this address will be consumed by the power management logic and decoded to MWAIT instructions. When IO port address redirection is enabled, this is the IO port address reported to the OS/software.
Definition at line 515 of file SilvermontMsr.h.
| UINT32 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER::Reserved1 |
Definition at line 524 of file SilvermontMsr.h.
| UINT32 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER::Reserved2 |
Definition at line 525 of file SilvermontMsr.h.
| UINT32 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER::Uint32 |
All bit fields as a 32-bit value
Definition at line 530 of file SilvermontMsr.h.
| UINT64 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER::Uint64 |
All bit fields as a 64-bit value
Definition at line 534 of file SilvermontMsr.h.