#include <MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h>

Data Fields
struct {
UINT32 EnMonitoring: 1

UINT32 EnExcept: 1

UINT32 EnLBRFrz: 1

UINT32 DisableInGuest: 1

UINT32 Reserved1: 4

UINT32 WindowSize: 10

UINT32 Reserved2: 6

UINT32 WindowCntSel: 2

UINT32 CntAndMode: 1

UINT32 Reserved3: 5

UINT32 Reserved4: 32

}	Bits

UINT32	Uint32

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SKYLAKE_BR_DETECT_CTRL

Definition at line 2672 of file SkylakeMsr.h.

Field Documentation

◆

struct { ... } MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::Bits

Individual bit fields

◆ CntAndMode

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::CntAndMode

[Bit 26] CntAndMode When set to '1', the overall branch monitoring event triggering condition is true only if all enabled counters' threshold conditions are true. When '0', the threshold tripping condition is true if any enabled counters' threshold is true.

Definition at line 2721 of file SkylakeMsr.h.

◆ DisableInGuest

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::DisableInGuest

[Bit 3] DisableInGuest When set to '1', branch monitoring, event triggering and LBR freeze actions are disabled when operating at VMX non-root operation.

Definition at line 2699 of file SkylakeMsr.h.

◆ EnExcept

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::EnExcept

[Bit 1] EnExcept Enable branch monitoring event signaling on threshold trip. The branch monitoring event handler is signaled via the existing PMI signaling mechanism as programmed from the corresponding local APIC LVT entry.

Definition at line 2687 of file SkylakeMsr.h.

◆ EnLBRFrz

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::EnLBRFrz

[Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a triggering condition occurs and this bit is enabled.

Definition at line 2693 of file SkylakeMsr.h.

◆ EnMonitoring

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::EnMonitoring

[Bit 0] EnMonitoring Global enable for branch monitoring.

Definition at line 2680 of file SkylakeMsr.h.

◆ Reserved1

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::Reserved1

Definition at line 2700 of file SkylakeMsr.h.

◆ Reserved2

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::Reserved2

Definition at line 2708 of file SkylakeMsr.h.

◆ Reserved3

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::Reserved3

Definition at line 2722 of file SkylakeMsr.h.

◆ Reserved4

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::Reserved4

Definition at line 2723 of file SkylakeMsr.h.

◆ Uint32

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 2728 of file SkylakeMsr.h.

◆ Uint64

UINT64 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 2732 of file SkylakeMsr.h.

◆ WindowCntSel

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::WindowCntSel

[Bits 25:24] WindowCntSel Window event count select: '00 = Instructions retired. '01 = Branch instructions retired '10 = Return instructions retired. '11 = Indirect branch instructions retired.

Definition at line 2714 of file SkylakeMsr.h.

◆ WindowSize

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::WindowSize

[Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 - 1023 are supported. Once the Window counter reaches the WindowSize count both the Window Counter and all Branch Monitoring Counters are cleared.

Definition at line 2707 of file SkylakeMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h

Data Fields