MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h>

Data Fields
struct {
UINT32   CBM: 20
UINT32   Reserved2: 12
UINT32   Reserved3: 32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N

Definition at line 3711 of file SkylakeMsr.h.

Field Documentation

struct { ... } MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER::Bits

Individual bit fields

CBM

UINT32 MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER::CBM

[Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.

Definition at line 3719 of file SkylakeMsr.h.

Reserved2

UINT32 MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER::Reserved2

Definition at line 3720 of file SkylakeMsr.h.

Reserved3

UINT32 MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER::Reserved3

Definition at line 3721 of file SkylakeMsr.h.

Uint32

UINT32 MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 3726 of file SkylakeMsr.h.

Uint64

UINT64 MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 3730 of file SkylakeMsr.h.

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The documentation for this union was generated from the following file:

• MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h