#include <MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h>

Data Fields
struct {
UINT32 Ovf_PMC0: 1

UINT32 Ovf_PMC1: 1

UINT32 Ovf_PMC2: 1

UINT32 Ovf_PMC3: 1

UINT32 Ovf_PMC4: 1

UINT32 Ovf_PMC5: 1

UINT32 Ovf_PMC6: 1

UINT32 Ovf_PMC7: 1

UINT32 Reserved1: 24

UINT32 Ovf_FixedCtr0: 1

UINT32 Ovf_FixedCtr1: 1

UINT32 Ovf_FixedCtr2: 1

UINT32 Reserved2: 20

UINT32 Trace_ToPA_PMI: 1

UINT32 Reserved3: 2

UINT32 LBR_Frz: 1

UINT32 CTR_Frz: 1

UINT32 ASCI: 1

UINT32 Ovf_Uncore: 1

UINT32 Ovf_BufDSSAVE: 1

UINT32 CondChgd: 1

}	Bits

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET

Definition at line 378 of file SkylakeMsr.h.

Field Documentation

◆ ASCI

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::ASCI

[Bit 60] Thread. Set 1 to clear ASCI.

Definition at line 445 of file SkylakeMsr.h.

◆

struct { ... } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Bits

Individual bit fields

◆ CondChgd

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CondChgd

[Bit 63] Thread. Set 1 to clear CondChgd.

Definition at line 457 of file SkylakeMsr.h.

◆ CTR_Frz

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CTR_Frz

[Bit 59] Thread. Set 1 to clear CTR_Frz.

Definition at line 441 of file SkylakeMsr.h.

◆ LBR_Frz

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::LBR_Frz

[Bit 58] Thread. Set 1 to clear LBR_Frz.

Definition at line 437 of file SkylakeMsr.h.

◆ Ovf_BufDSSAVE

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_BufDSSAVE

[Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.

Definition at line 453 of file SkylakeMsr.h.

◆ Ovf_FixedCtr0

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FixedCtr0

[Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.

Definition at line 419 of file SkylakeMsr.h.

◆ Ovf_FixedCtr1

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FixedCtr1

[Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.

Definition at line 423 of file SkylakeMsr.h.

◆ Ovf_FixedCtr2

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FixedCtr2

[Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.

Definition at line 427 of file SkylakeMsr.h.

◆ Ovf_PMC0

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC0

[Bit 0] Thread. Set 1 to clear Ovf_PMC0.

Definition at line 386 of file SkylakeMsr.h.

◆ Ovf_PMC1

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC1

[Bit 1] Thread. Set 1 to clear Ovf_PMC1.

Definition at line 390 of file SkylakeMsr.h.

◆ Ovf_PMC2

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC2

[Bit 2] Thread. Set 1 to clear Ovf_PMC2.

Definition at line 394 of file SkylakeMsr.h.

◆ Ovf_PMC3

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC3

[Bit 3] Thread. Set 1 to clear Ovf_PMC3.

Definition at line 398 of file SkylakeMsr.h.

◆ Ovf_PMC4

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC4

[Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).

Definition at line 402 of file SkylakeMsr.h.

◆ Ovf_PMC5

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC5

[Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).

Definition at line 406 of file SkylakeMsr.h.

◆ Ovf_PMC6

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC6

[Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).

Definition at line 410 of file SkylakeMsr.h.

◆ Ovf_PMC7

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC7

[Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).

Definition at line 414 of file SkylakeMsr.h.

◆ Ovf_Uncore

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_Uncore

[Bit 61] Thread. Set 1 to clear Ovf_Uncore.

Definition at line 449 of file SkylakeMsr.h.

◆ Reserved1

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Reserved1

Definition at line 415 of file SkylakeMsr.h.

◆ Reserved2

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Reserved2

Definition at line 428 of file SkylakeMsr.h.

◆ Reserved3

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Reserved3

Definition at line 433 of file SkylakeMsr.h.

◆ Trace_ToPA_PMI

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Trace_ToPA_PMI

[Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.

Definition at line 432 of file SkylakeMsr.h.

◆ Uint64

UINT64 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 462 of file SkylakeMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h

Data Fields