#include <MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h>

Data Fields
struct {
UINT32 EventID: 8

UINT32 Reserved1: 24

UINT32 RMID: 10

UINT32 Reserved2: 22

}	Bits

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SKYLAKE_IA32_QM_EVTSEL

Definition at line 3605 of file SkylakeMsr.h.

Field Documentation

◆

struct { ... } MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER::Bits

Individual bit fields

◆ EventID

UINT32 MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER::EventID

[Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3 occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03: Local memory bandwidth monitoring. All other encoding reserved.

Definition at line 3615 of file SkylakeMsr.h.

◆ Reserved1

UINT32 MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER::Reserved1

Definition at line 3616 of file SkylakeMsr.h.

◆ Reserved2

UINT32 MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER::Reserved2

Definition at line 3621 of file SkylakeMsr.h.

◆ RMID

UINT32 MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER::RMID

[Bits 41:32] RMID (RW).

Definition at line 3620 of file SkylakeMsr.h.

◆ Uint64

UINT64 MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 3626 of file SkylakeMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h

Data Fields