TianoCore EDK2 master
Loading...
Searching...
No Matches
Data Fields
MSR_SKYLAKE_PLATFORM_INFO_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h>

Data Fields

struct {
   UINT32   Reserved1: 8
 
   UINT32   MaximumNon_TurboRatio: 8
 
   UINT32   Reserved2: 7
 
   UINT32   PPIN_CAP: 1
 
   UINT32   Reserved3: 4
 
   UINT32   ProgrammableRatioLimit: 1
 
   UINT32   ProgrammableTDPLimit: 1
 
   UINT32   ProgrammableTJOFFSET: 1
 
   UINT32   Reserved4: 1
 
   UINT32   Reserved5: 8
 
   UINT32   MaximumEfficiencyRatio: 8
 
   UINT32   Reserved6: 16
 
} Bits
 
UINT64 Uint64
 

Detailed Description

MSR information returned for MSR index MSR_SKYLAKE_PLATFORM_INFO

Definition at line 2971 of file SkylakeMsr.h.

Field Documentation

◆ 

struct { ... } MSR_SKYLAKE_PLATFORM_INFO_REGISTER::Bits

Individual bit fields

◆ MaximumEfficiencyRatio

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::MaximumEfficiencyRatio

[Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.

Definition at line 3006 of file SkylakeMsr.h.

◆ MaximumNon_TurboRatio

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::MaximumNon_TurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.

Definition at line 2980 of file SkylakeMsr.h.

◆ PPIN_CAP

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::PPIN_CAP

[Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.

Definition at line 2985 of file SkylakeMsr.h.

◆ ProgrammableRatioLimit

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::ProgrammableRatioLimit

[Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See Table 2-25.

Definition at line 2991 of file SkylakeMsr.h.

◆ ProgrammableTDPLimit

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::ProgrammableTDPLimit

[Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See Table 2-25.

Definition at line 2996 of file SkylakeMsr.h.

◆ ProgrammableTJOFFSET

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::ProgrammableTJOFFSET

[Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.

Definition at line 3000 of file SkylakeMsr.h.

◆ Reserved1

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::Reserved1

Definition at line 2976 of file SkylakeMsr.h.

◆ Reserved2

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::Reserved2

Definition at line 2981 of file SkylakeMsr.h.

◆ Reserved3

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::Reserved3

Definition at line 2986 of file SkylakeMsr.h.

◆ Reserved4

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::Reserved4

Definition at line 3001 of file SkylakeMsr.h.

◆ Reserved5

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::Reserved5

Definition at line 3002 of file SkylakeMsr.h.

◆ Reserved6

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::Reserved6

Definition at line 3007 of file SkylakeMsr.h.

◆ Uint64

UINT64 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 3012 of file SkylakeMsr.h.

The documentation for this union was generated from the following file: