MSR_SKYLAKE_PPIN_CTL_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h>

Data Fields
struct {
UINT32   LockOut: 1
UINT32   Enable_PPIN: 1
UINT32   Reserved1: 30
UINT32   Reserved2: 32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SKYLAKE_PPIN_CTL

Definition at line 2905 of file SkylakeMsr.h.

Field Documentation

struct { ... } MSR_SKYLAKE_PPIN_CTL_REGISTER::Bits

Individual bit fields

Enable_PPIN

UINT32 MSR_SKYLAKE_PPIN_CTL_REGISTER::Enable_PPIN

[Bit 1] Enable_PPIN (R/W) See Table 2-25.

Definition at line 2917 of file SkylakeMsr.h.

LockOut

UINT32 MSR_SKYLAKE_PPIN_CTL_REGISTER::LockOut

[Bit 0] LockOut (R/WO) See Table 2-25.

Definition at line 2913 of file SkylakeMsr.h.

Reserved1

UINT32 MSR_SKYLAKE_PPIN_CTL_REGISTER::Reserved1

Definition at line 2918 of file SkylakeMsr.h.

Reserved2

UINT32 MSR_SKYLAKE_PPIN_CTL_REGISTER::Reserved2

Definition at line 2919 of file SkylakeMsr.h.

Uint32

UINT32 MSR_SKYLAKE_PPIN_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 2924 of file SkylakeMsr.h.

Uint64

UINT64 MSR_SKYLAKE_PPIN_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 2928 of file SkylakeMsr.h.

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The documentation for this union was generated from the following file:

• MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h