MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h>

Data Fields
struct {
UINT32   Maximum1C: 8
UINT32   Maximum2C: 8
UINT32   Maximum3C: 8
UINT32   Maximum4C: 8
UINT32   Reserved: 32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SKYLAKE_TURBO_RATIO_LIMIT

Definition at line 67 of file SkylakeMsr.h.

Field Documentation

struct { ... } MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

Maximum1C

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Maximum1C

[Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active.

Definition at line 76 of file SkylakeMsr.h.

Maximum2C

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Maximum2C

[Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active.

Definition at line 81 of file SkylakeMsr.h.

Maximum3C

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Maximum3C

[Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active.

Definition at line 86 of file SkylakeMsr.h.

Maximum4C

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Maximum4C

[Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active.

Definition at line 91 of file SkylakeMsr.h.

Reserved

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Reserved

Definition at line 92 of file SkylakeMsr.h.

Uint32

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 97 of file SkylakeMsr.h.

Uint64

UINT64 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 101 of file SkylakeMsr.h.

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The documentation for this union was generated from the following file:

• MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h