MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h>

Data Fields
struct {
UINT32   Reserved1: 10
UINT32   Fix_Me_1: 1
UINT32   Fix_Me_2: 1
UINT32   Reserved2: 20
UINT32   Reserved3: 32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK

Definition at line 2569 of file SkylakeMsr.h.

Field Documentation

struct { ... } MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Bits

Individual bit fields

Fix_Me_1

UINT32 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Fix_Me_1

[Bit 10] Lock Setting this bit locks all writeable settings in this register, including itself.

Definition at line 2579 of file SkylakeMsr.h.

Fix_Me_2

UINT32 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Fix_Me_2

[Bit 11] Range_En Indicates whether the PRMRR range is enabled and valid.

Definition at line 2584 of file SkylakeMsr.h.

Reserved1

UINT32 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Reserved1

Definition at line 2574 of file SkylakeMsr.h.

Reserved2

UINT32 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Reserved2

Definition at line 2585 of file SkylakeMsr.h.

Reserved3

UINT32 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Reserved3

Definition at line 2586 of file SkylakeMsr.h.

Uint32

UINT32 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 2591 of file SkylakeMsr.h.

Uint64

UINT64 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 2595 of file SkylakeMsr.h.

---

The documentation for this union was generated from the following file:

• MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h