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MSR_XEON_5600_FEATURE_CONFIG_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h>

Data Fields

struct {
   UINT32   AESConfiguration: 2
 
   UINT32   Reserved1: 30
 
   UINT32   Reserved2: 32
 
Bits
 
UINT32 Uint32
 
UINT64 Uint64
 

Detailed Description

MSR information returned for MSR index MSR_XEON_5600_FEATURE_CONFIG

Definition at line 64 of file Xeon5600Msr.h.

Field Documentation

◆ AESConfiguration

UINT32 MSR_XEON_5600_FEATURE_CONFIG_REGISTER::AESConfiguration

[Bits 1:0] AES Configuration (RW-L) Upon a successful read of this MSR, the configuration of AES instruction set availability is as follows: 11b: AES instructions are not available until next RESET. otherwise, AES instructions are available. Note, AES instruction set is not available if read is unsuccessful. If the configuration is not 01b, AES instruction can be mis-configured if a privileged agent unintentionally writes 11b.

Definition at line 78 of file Xeon5600Msr.h.

◆ 

struct { ... } MSR_XEON_5600_FEATURE_CONFIG_REGISTER::Bits

Individual bit fields

◆ Reserved1

UINT32 MSR_XEON_5600_FEATURE_CONFIG_REGISTER::Reserved1

Definition at line 79 of file Xeon5600Msr.h.

◆ Reserved2

UINT32 MSR_XEON_5600_FEATURE_CONFIG_REGISTER::Reserved2

Definition at line 80 of file Xeon5600Msr.h.

◆ Uint32

UINT32 MSR_XEON_5600_FEATURE_CONFIG_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 85 of file Xeon5600Msr.h.

◆ Uint64

UINT64 MSR_XEON_5600_FEATURE_CONFIG_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 89 of file Xeon5600Msr.h.


The documentation for this union was generated from the following file: