#include <MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h>

Data Fields
struct {
UINT32 Maximum1C: 8

UINT32 Maximum2C: 8

UINT32 Maximum3C: 8

UINT32 Maximum4C: 8

UINT32 Maximum5C: 8

UINT32 Maximum6C: 8

UINT32 Reserved: 16

}	Bits

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER

Definition at line 133 of file Xeon5600Msr.h.

Field Documentation

◆

struct { ... } MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

◆ Maximum1C

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Maximum1C

[Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active.

Definition at line 142 of file Xeon5600Msr.h.

◆ Maximum2C

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Maximum2C

[Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active.

Definition at line 147 of file Xeon5600Msr.h.

◆ Maximum3C

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Maximum3C

[Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active.

Definition at line 152 of file Xeon5600Msr.h.

◆ Maximum4C

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Maximum4C

[Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active.

Definition at line 157 of file Xeon5600Msr.h.

◆ Maximum5C

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Maximum5C

[Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio limit of 5 core active.

Definition at line 162 of file Xeon5600Msr.h.

◆ Maximum6C

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Maximum6C

[Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio limit of 6 core active.

Definition at line 167 of file Xeon5600Msr.h.

◆ Reserved

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Reserved

Definition at line 168 of file Xeon5600Msr.h.

◆ Uint64

UINT64 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 173 of file Xeon5600Msr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h

Data Fields