#include <MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h>

Data Fields
struct {
UINT32 PROCHOT_Status: 1

UINT32 ThermalStatus: 1

UINT32 Reserved1: 4

UINT32 VRThermAlertStatus: 1

UINT32 Reserved2: 1

UINT32 ElectricalDesignPointStatus: 1

UINT32 Reserved3: 23

UINT32 Reserved4: 32

}	Bits

UINT32	Uint32

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS

Definition at line 1594 of file XeonPhiMsr.h.

Field Documentation

◆

struct { ... } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::Bits

Individual bit fields

◆ ElectricalDesignPointStatus

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointStatus

[Bit 8] Electrical Design Point Status (R0).

Definition at line 1616 of file XeonPhiMsr.h.

◆ PROCHOT_Status

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Status

[Bit 0] PROCHOT Status (R0).

Definition at line 1602 of file XeonPhiMsr.h.

◆ Reserved1

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::Reserved1

Definition at line 1607 of file XeonPhiMsr.h.

◆ Reserved2

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::Reserved2

Definition at line 1612 of file XeonPhiMsr.h.

◆ Reserved3

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::Reserved3

Definition at line 1617 of file XeonPhiMsr.h.

◆ Reserved4

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::Reserved4

Definition at line 1618 of file XeonPhiMsr.h.

◆ ThermalStatus

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalStatus

[Bit 1] Thermal Status (R0).

Definition at line 1606 of file XeonPhiMsr.h.

◆ Uint32

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 1623 of file XeonPhiMsr.h.

◆ Uint64

UINT64 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 1627 of file XeonPhiMsr.h.

◆ VRThermAlertStatus

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus

[Bit 6] VR Therm Alert Status (R0).

Definition at line 1611 of file XeonPhiMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h

Data Fields