#include <MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h>

Data Fields
struct {
UINT32 AESConfiguration: 2

UINT32 Reserved1: 30

UINT32 Reserved2: 32

}	Bits

UINT32	Uint32

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_FEATURE_CONFIG

Definition at line 379 of file XeonPhiMsr.h.

Field Documentation

◆ AESConfiguration

UINT32 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER::AESConfiguration

[Bits 1:0] AES Configuration (RW-L) Upon a successful read of this MSR, the configuration of AES instruction set availability is as follows: 11b: AES instructions are not available until next RESET. otherwise, AES instructions are available. Note, AES instruction set is not available if read is unsuccessful. If the configuration is not 01b, AES instruction can be mis-configured if a privileged agent unintentionally writes 11b.

Definition at line 393 of file XeonPhiMsr.h.

◆

struct { ... } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER::Bits

Individual bit fields

◆ Reserved1

UINT32 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER::Reserved1

Definition at line 394 of file XeonPhiMsr.h.

◆ Reserved2

UINT32 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER::Reserved2

Definition at line 395 of file XeonPhiMsr.h.

◆ Uint32

UINT32 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 400 of file XeonPhiMsr.h.

◆ Uint64

UINT64 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 404 of file XeonPhiMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h

Data Fields