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Data Fields
MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h>

Data Fields

struct {
   UINT32   FastStrings: 1
 
   UINT32   Reserved1: 2
 
   UINT32   AutomaticThermalControlCircuit: 1
 
   UINT32   Reserved2: 3
 
   UINT32   PerformanceMonitoring: 1
 
   UINT32   Reserved3: 3
 
   UINT32   BTS: 1
 
   UINT32   PEBS: 1
 
   UINT32   Reserved4: 3
 
   UINT32   EIST: 1
 
   UINT32   Reserved5: 1
 
   UINT32   MONITOR: 1
 
   UINT32   Reserved6: 3
 
   UINT32   LimitCpuidMaxval: 1
 
   UINT32   xTPR_Message_Disable: 1
 
   UINT32   Reserved7: 8
 
   UINT32   Reserved8: 2
 
   UINT32   XD: 1
 
   UINT32   Reserved9: 3
 
   UINT32   TurboModeDisable: 1
 
   UINT32   Reserved10: 25
 
} Bits
 
UINT64 Uint64
 

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_IA32_MISC_ENABLE

Definition at line 546 of file XeonPhiMsr.h.

Field Documentation

◆ AutomaticThermalControlCircuit

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value is 1.

Definition at line 560 of file XeonPhiMsr.h.

◆ 

struct { ... } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

◆ BTS

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Branch Trace Storage Unavailable (RO).

Definition at line 570 of file XeonPhiMsr.h.

◆ EIST

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).

Definition at line 579 of file XeonPhiMsr.h.

◆ FastStrings

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Fast-Strings Enable.

Definition at line 554 of file XeonPhiMsr.h.

◆ LimitCpuidMaxval

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Limit CPUID Maxval (R/W).

Definition at line 589 of file XeonPhiMsr.h.

◆ MONITOR

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] ENABLE MONITOR FSM (R/W).

Definition at line 584 of file XeonPhiMsr.h.

◆ PEBS

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Processor Event Based Sampling Unavailable (RO).

Definition at line 574 of file XeonPhiMsr.h.

◆ PerformanceMonitoring

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Performance Monitoring Available (R).

Definition at line 565 of file XeonPhiMsr.h.

◆ Reserved1

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved1

Definition at line 555 of file XeonPhiMsr.h.

◆ Reserved10

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved10

Definition at line 605 of file XeonPhiMsr.h.

◆ Reserved2

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved2

Definition at line 561 of file XeonPhiMsr.h.

◆ Reserved3

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved3

Definition at line 566 of file XeonPhiMsr.h.

◆ Reserved4

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved4

Definition at line 575 of file XeonPhiMsr.h.

◆ Reserved5

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved5

Definition at line 580 of file XeonPhiMsr.h.

◆ Reserved6

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved6

Definition at line 585 of file XeonPhiMsr.h.

◆ Reserved7

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved7

Definition at line 594 of file XeonPhiMsr.h.

◆ Reserved8

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved8

Definition at line 595 of file XeonPhiMsr.h.

◆ Reserved9

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Reserved9

Definition at line 600 of file XeonPhiMsr.h.

◆ TurboModeDisable

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::TurboModeDisable

[Bit 38] Turbo Mode Disable (R/W).

Definition at line 604 of file XeonPhiMsr.h.

◆ Uint64

UINT64 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 610 of file XeonPhiMsr.h.

◆ XD

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] XD Bit Disable (R/W).

Definition at line 599 of file XeonPhiMsr.h.

◆ xTPR_Message_Disable

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] xTPR Message Disable (R/W).

Definition at line 593 of file XeonPhiMsr.h.

The documentation for this union was generated from the following file: