MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Union Reference

#include <MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h>

Data Fields
struct {
UINT32   DCUHardwarePrefetcherDisable: 1
UINT32   L2HardwarePrefetcherDisable: 1
UINT32   Reserved1: 30
UINT32   Reserved2: 32
}	Bits
UINT32	Uint32
UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_MISC_FEATURE_CONTROL

Definition at line 686 of file XeonPhiMsr.h.

Field Documentation

struct { ... } MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

DCUHardwarePrefetcherDisable

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::DCUHardwarePrefetcherDisable

[Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher.

Definition at line 695 of file XeonPhiMsr.h.

L2HardwarePrefetcherDisable

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::L2HardwarePrefetcherDisable

[Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher.

Definition at line 700 of file XeonPhiMsr.h.

Reserved1

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Reserved1

Definition at line 701 of file XeonPhiMsr.h.

Reserved2

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Reserved2

Definition at line 702 of file XeonPhiMsr.h.

Uint32

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 707 of file XeonPhiMsr.h.

Uint64

UINT64 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 711 of file XeonPhiMsr.h.

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The documentation for this union was generated from the following file:

• MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h