#include <MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h>

Data Fields
struct {
UINT32 Reserved1: 1

UINT32 UserModeMonitorAndMwait: 1

UINT32 Reserved2: 30

UINT32 Reserved3: 32

}	Bits

UINT32	Uint32

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_MISC_FEATURE_ENABLES

Definition at line 429 of file XeonPhiMsr.h.

Field Documentation

◆

struct { ... } MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER::Bits

Individual bit fields

◆ Reserved1

UINT32 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER::Reserved1

Definition at line 434 of file XeonPhiMsr.h.

◆ Reserved2

UINT32 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER::Reserved2

Definition at line 444 of file XeonPhiMsr.h.

◆ Reserved3

UINT32 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER::Reserved3

Definition at line 445 of file XeonPhiMsr.h.

◆ Uint32

UINT32 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 450 of file XeonPhiMsr.h.

◆ Uint64

UINT64 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 454 of file XeonPhiMsr.h.

◆ UserModeMonitorAndMwait

UINT32 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER::UserModeMonitorAndMwait

[Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and MWAIT instructions do not cause invalid-opcode exceptions when executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state other than C0 or C1, the instruction operates as if EAX indicated the C-state C1.

Definition at line 443 of file XeonPhiMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h

Data Fields