TianoCore EDK2 master
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#include <MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h>
Data Fields | |
struct { | |
UINT32 Limit: 3 | |
UINT32 Reserved1: 7 | |
UINT32 IO_MWAIT: 1 | |
UINT32 Reserved2: 4 | |
UINT32 CFGLock: 1 | |
UINT32 Reserved5: 10 | |
UINT32 C1StateAutoDemotionEnable: 1 | |
UINT32 Reserved6: 1 | |
UINT32 C1StateAutoUndemotionEnable: 1 | |
UINT32 PKGC_StateAutoDemotionEnable: 1 | |
UINT32 Reserved7: 2 | |
UINT32 Reserved4: 32 | |
} | Bits |
UINT32 | Uint32 |
UINT64 | Uint64 |
MSR information returned for MSR index MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL
Definition at line 252 of file XeonPhiMsr.h.
struct { ... } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Bits |
Individual bit fields
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::C1StateAutoDemotionEnable |
[Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information.
Definition at line 279 of file XeonPhiMsr.h.
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::C1StateAutoUndemotionEnable |
[Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables Undemotion from Demoted C1.
Definition at line 285 of file XeonPhiMsr.h.
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::CFGLock |
[Bit 15] CFG Lock (R/WO).
Definition at line 272 of file XeonPhiMsr.h.
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::IO_MWAIT |
[Bit 10] I/O MWAIT Redirection Enable (R/W).
Definition at line 267 of file XeonPhiMsr.h.
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Limit |
[Bits 2:0] Package C-State Limit (R/W) The following C-state code name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No Retention 011b: C6 Retention 111b: No limit.
Definition at line 262 of file XeonPhiMsr.h.
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::PKGC_StateAutoDemotionEnable |
[Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables Package C state demotion.
Definition at line 290 of file XeonPhiMsr.h.
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Reserved1 |
Definition at line 263 of file XeonPhiMsr.h.
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Reserved2 |
Definition at line 268 of file XeonPhiMsr.h.
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Reserved4 |
Definition at line 292 of file XeonPhiMsr.h.
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Reserved5 |
Definition at line 273 of file XeonPhiMsr.h.
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Reserved6 |
Definition at line 280 of file XeonPhiMsr.h.
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Reserved7 |
Definition at line 291 of file XeonPhiMsr.h.
UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Uint32 |
All bit fields as a 32-bit value
Definition at line 297 of file XeonPhiMsr.h.
UINT64 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Uint64 |
All bit fields as a 64-bit value
Definition at line 301 of file XeonPhiMsr.h.