#include <MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h>

Data Fields
struct {
UINT32 Lvl2Base: 16

UINT32 CStateRange: 7

UINT32 Reserved3: 9

UINT32 Reserved2: 32

}	Bits

UINT32	Uint32

UINT64	Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_PHI_PMG_IO_CAPTURE_BASE

Definition at line 327 of file XeonPhiMsr.h.

Field Documentation

◆

struct { ... } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER::Bits

Individual bit fields

◆ CStateRange

UINT32 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER::CStateRange

[Bits 22:16] C-State Range (R/W) The IO-port block size in which IO-redirection will be executed (0-127). Should be programmed based on the number of LVLx registers existing in the chipset.

Definition at line 341 of file XeonPhiMsr.h.

◆ Lvl2Base

UINT32 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER::Lvl2Base

[Bits 15:0] LVL_2 Base Address (R/W).

Definition at line 335 of file XeonPhiMsr.h.

◆ Reserved2

UINT32 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER::Reserved2

Definition at line 343 of file XeonPhiMsr.h.

◆ Reserved3

UINT32 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER::Reserved3

Definition at line 342 of file XeonPhiMsr.h.

◆ Uint32

UINT32 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER::Uint32

All bit fields as a 32-bit value

Definition at line 348 of file XeonPhiMsr.h.

◆ Uint64

UINT64 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER::Uint64

All bit fields as a 64-bit value

Definition at line 352 of file XeonPhiMsr.h.

The documentation for this union was generated from the following file:

MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h

Data Fields